21-01-2016, 02:38 PM
Abstract
The need for high performance decimal arithmetic is required in many applications. Using binary system to process decimal numbers tends to be costly in terms of area and speed. Hence, there is a demand to realize decimal operations efficiently. In this paper, an improved approach to implement decimal addition is proposed. A hardware implementation of this arithmetic function is developed based on 6-input LUTs and the fast carry chains. In our proposed approach, a new architecture of a BCD adder is presented with emphasis on critical path delay reduction. The adder architecture has been implemented on Xilinx Virtex-6 FPGA for operand sizes from 2 to 18 digits. Our design has outperformed other approaches in terms of area and delay. On average, the delay reduction is 13.1% and LUT saving is 28.9% compared to a conventional BCD adder.
INTRODUCTION
Decimal computations are required in various applications, such as internet, industrial control, financial and commercial systems. Recently there is an increasing demand for efficient hardware realizations required in these applications. This has also led to the specification revision of the IEEE-754-2008 standard for floating-point arithmetic to incorporate the decimal format [1-2]. As in any hardware realization of real time systems, there is always a requirement to achieve high performance at a low cost. However, decimal arithmetic architectures and the hardware realizations, particularly, in Field Programmable Gate Arrays (FPGAs) have not been fully tackled in the literature. Therefore, efficient methods for the implementation of decimal operations are receiving more attention from hardware designers. In decimal computation, the most common operation is addition. Earlier decimal adders were designed at the gate level targeting ASICs [3-6]. Binary-Coded-Decimal (BCD) number representation was used in these designs. Some schemes utilized in binary adders were also employed in these BCD additions. In [3], a reduced delay BCD adder was proposed. This approach improved the delay of BCD addition by increasing parallelism. Two 4-bit binary adders, a carry circuit, one AND gate, and one OR gate were used in the critical-path of the adder. In [5], a BCD adder was realized using reversible logic gates. Carry Look-Ahead scheme was employed to speed up the performance. The author in [6] proposed a multi-operand parallel decimal adder, which involved binary to decimal conversion in order to obtain BCD result. The conversion allows for an easy alignment of the sums of adjacent columns. Fast carry free adders and parallel conversions were used in this BCD adder approach. With the advancement in FPGA technology, the efficiency of the architecture, and availability of various hardware resources, decimal arithmetic can be implemented with high degree of efficiency. In [7] decimal adders/subtractors were proposed based on the use of Look Up Tables (LUTs) in FPGAs. In [8] a multi-operand decimal adder trees were presented and optimized based on the 6-input LUTs with the fast carry chains. Carry-ripple BCD adders were used in the adder tree, which led to an increase in the critical path delay. In this paper, an improved carry-ripple BCD adder is presented targeting critical path delay reduction. When implemented into Xilinx’ Virtex-6 FPGA, we achieved both speed improvement and area reduction. The organization of this paper is as follows. Section 2 introduces some existing decimal adders that were used in this paper for comparison purpose. The improved BCD adder approach is presented in Section 3. In Section 4, the implementations and comparison of results are described, and the conclusions are given in the last section.