01-10-2014, 11:27 AM
An Improved BCD Adder Using 6-LUT FPGAs
An Improved BCD.pdf (Size: 573.08 KB / Downloads: 109)
Abstract
The need for high performance decimal arithmetic
is required in many applications. Using binary system to process
decimal numbers tends to be costly in terms of area and speed.
Hence, there is a demand to realize decimal operations
efficiently. In this paper, an improved approach to implement
decimal addition is proposed. A hardware implementation of
this arithmetic function is developed based on 6-input LUTs and
the fast carry chains. In our proposed approach, a new
architecture of a BCD adder is presented with emphasis on
critical path delay reduction. The adder architecture has been
implemented on Xilinx Virtex-6 FPGA for operand sizes from 2
to 18 digits. Our design has outperformed other approaches in
terms of area and delay. On average, the delay reduction is
13.1% and LUT saving is 28.9% compared to a conventional
BCD adder.
INTRODUCTION
Decimal computations are required in various applications,
such as internet, industrial control, financial and commercial
systems. Recently there is an increasing demand for efficient
hardware realizations required in these applications. This has
also led to the specification revision of the IEEE-754-2008
standard for floating-point arithmetic to incorporate the
decimal format [1-2].
As in any hardware realization of real time systems, there
is always a requirement to achieve high performance at a low
cost. However, decimal arithmetic architectures and the
hardware realizations, particularly, in Field Programmable
Gate Arrays (FPGAs) have not been fully tackled in the
literature. Therefore, efficient methods for the implementation
of decimal operations are receiving more attention from
hardware designers.
RELATED BCD ADDITIONS
In this section we will describe three BCD adder
architectures that we have implemented and compared with
our proposed scheme
RELATED BCD ADDITIONS
In this section we will describe three BCD adder
architectures that we have implemented and compared with
our proposed scheme
PROPOSED BCD ADDER
The proposed BCD adder is also based on 6-input LUTs
and the fast carry chains in FPGAs. Assume the input
operands of the adder are A and B in BCD format. To use the
6-input LUTs, each of the two input operands is decomposed
into two parts:
A =[a3a2a1a0]= (a3a2a1)×2 + a0
= A1×2 + a0
B =[b3b2b1b0]= (b3b2b1)×2 + b0
= B1×2 +b0
The output of the BCD adder, named as (Cout S3S2S1S0), is
presented as:
[Cout S3S2S1S0]= A + B + Cin
=[A1×2+a0]+ [B1×2+b0]+Cin
=[(a3a2a1)+(b3b2b1)]×2+[a0+b0+Cin] (4)
In (4), the expression in the first part represents a 3-bit adder,
and the expression in the second part is a full adder. Since the
input operands in (4) are BCD numbers, the maximum value
of the operands, (a3a2a1) or (b3b2b1) is (100)2. To achieve a
BCD output, an adding-3 correction is performed based on the
sum of (A1+B1) and the carry of the full adder, named as C1.
Thus, the output of the BCD adder is expressed as:
IMPLEMENTATION OF THE BCD ADDERS
To illustrate the efficiency of the improved 6-LUT-based
BCD adder, the 1-digit BCD adder is designed as shown in
Fig. 6 and used as a basic block for 2- to 18-digit ripple carry
BCD adders. The other three adder architectures described in
Section II were also coded and implemented targeting the
same platform. The result of the improved adder is compared
with other three adder schemes. The implementations targeted
Xilinx’ Virtex-6 FPGA, 6vlx75tff784, with the speed of -3
[10] using ISE 13.1tools. The timing results were extracted
from the Post Placement-&-Routing Static Timing Report and
the LUTs usages were achieved from Place-&-Routing
Report. In order to obtain the timing information that is
focused on the actual circuit designed, all input and output
operands are double registered. Also, to achieve exact LUT
usage required for the designs, number of LUTs used for logic
is counted based on the implementation. Fig. 7 depicts the
results in terms of delay and Fig. 8 illustrates the number of
LUTs used.
CONCLUSIONS
This paper presented an improved BCD adder based on
newer Xilinx FPGA architectures. The proposed BCD adder
approach efficiently mapped the decimal addition function
onto the 6-input LUTs and the fast carry chains in FPGAs.
The critical path of the adder has been minimized by
bypassing two multiplexers from incoming carry to outgoing
carry in the 1-digit BCD adder. The implementation of the
proposed approach has resulted in improvements in terms of
delay reduction and savings in the number of LUTs.