22-11-2012, 05:24 PM
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC
An On-Chip AHB Bus Tracer.pdf (Size: 1.82 MB / Downloads: 73)
Abstract
This paper proposes a multiresolution AHB on-chip
bus tracer named SYS-HMRBT (aHb multiresolution bus tracer)
for versatile system-on-chip (SoC) debugging and monitoring.
The bus tracer is capable of capturing the bus trace with different
resolutions, all with efficient built-in compression mechanisms,
to meet a diverse range of needs. In addition, it allows users
to switch the trace resolution dynamically so that appropriate
resolution levels can be applied to different segments of the trace.
On the other hand, SYS-HMRBT supports tracing after/before
an event triggering, named post-triggering trace/pre-triggering
trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K
gates in TSMC 0.13- m technology, indicating that it is capable of
real time tracing and is very small in modern SoCs. Experiments
show that the bus tracer achieves very good compression ratios of
79%–96%, depending on the selected resolution mode. As a case
study, it has been integrated into a 3-D graphics SoC to facilitate
the debugging and monitoring of the system behaviors. The SoC
has been successfully verified both in field-programmable gate
array and a test chip.
INTRODUCTION
THE ON-CHIP bus is an important system-on-chip (SoC)
infrastructure that connects major hardware components.
Monitoring the on-chip bus signals is crucial to the SoC debugging
and performance analysis/optimization. Unfortunately,
such signals are difficult to observe since they are deeply embedded
in a SoC and there are often no sufficient I/O pins to
access these signals. Therefore, a straightforward approach is
to embed a bus tracer in SoC to capture the bus signal trace and
store the trace in an on-chip storage such as the trace memory
which could then be off loaded to outside world (the trace analyzer
software) for analysis.
Unfortunately, the size of the bus trace grows rapidly. For example,
to capture AMBA AHB 2.0 [1] bus signals running at
200 MHz, the trace grows at 2 to 3 GB/s. Therefore, it is highly
desirable to compress the trace on the fly in order to reduce the
trace size. However, simply capturing/compressing bus signals
is not sufficient for SoC debugging and analysis, since the debugging/
analysis needs are versatile: some designers need all
signals at cycle-level, while some others only care about the
transactions. For the latter case, tracing all signals at cycle-level
wastes a lot of trace memory. Thus, there must be a way to capture
traces at different abstraction levels based on the specific
debugging/analysis need.
RELATED WORK
Since the huge trace size limits the trace depth in a trace
memory, there are hardware approaches to compress the traces.
The approaches can be divided into lossy and lossless trace compression.
The lossy trace compression approach achieves high compression
ratio by sacrificing the accuracy; the original signals
cannot be reconstructed from the trace. The purpose of this approach
is to identify if a problem occurs. Anis and Nicolici
[2] use the multiple input signature register (MISR) to perform
lossy compression. The results are stored in a trace memory
and compared with the golden patterns to locate the range of
the erroneous signals. The locating needs rerunning the system
several times with finer and finer resolution until the size of
the search range can fit in the trace memory. Such approach
is suitable for deterministic and repeatable system behaviors.
However, for a complex SoC with multiple independent IPs, the
on-chip bus activities are usually not deterministic and repeatable.
Therefore, lossless compression approaches are more appropriate
for realtime on-chip bus tracing.
Trace Direction: Pre-T/Post-T Trace
Supporting both trace directions provides the flexible debugging
strategies. As Fig. 4 shows, the post-T trace captures signals
after a triggering event, while the pre-T trace captures signals
before the triggering event. The post-T trace is usually used
to observe signals after a known event. The pre-T trace is useful
for diagnosing the causes of unexpected errors by capturing the
signals before the errors.
The mechanisms of the pre-T trace and the post-T trace are
different. The Post-T trace is simpler since the start time and
the stop time are known. It is activated when the target event
is matched and is turned off when the trace buffer is full. On
the other hand, the stop time of the pre-T trace is unpredictable.
The solution is to start tracing as soon as system reset (or some
other turning-on event). When the trace buffer is full, the new
trace data wrap around the trace buffer, which means the oldest
data are sacrificed for the newest ones.
Wrapping around the trace buffer causes a problem when the
trace needs to be compressed. Typical lossless compression algorithms
work by storing some initial (previous) states of the
trace first and then calculate the relationship between the current
data and the previous states. Since the size of the relationship is
smaller than the data size, e.g., the difference, it saves spaces.
EXPERIMENTAL RESULTS
The specification of the implemented SYS-HMRBT bus
tracer is shown in Table V. It has been implemented at C,
RTL, FPGA, and chip levels. The synthesis result with TSMC
0.13- technology is shown in Table VI. The bus tracer costs
only about 41 K gates, which is relatively small in a typical
SoC. The largest component is the FIFO buffer in the packing
module. The second one is the compression module. The cost
to support both the pre-T and post-T capabilities (periodical
triggering module) is only 1032 gates. The major component
of the event generation module is the event register, which is
roughly 1500 gates per register. The implementation in this
paper has two event registers. More registers can be added if
necessary. Compared with our previous work [13], the gate
count is reduced by 31%.
CONCLUSION
We have presented an on-chip bus tracer SYS-HMRBT
for the development, integration, debugging, monitoring, and
tuning of AHB-based SoC’s. It is attached to the on-chip AHB
bus and is capable of capturing and compressing in real time
the bus traces with five modes of resolution. These modes
could be dynamically switched while tracing. The bus tracer
also supports both directions of traces: pre-T trace (trace before
the triggering event) and post-T trace (trace after the triggering
event). In addition, a graphical user interface, running on
a host PC, has been developed to configure the bus tracer
and analyze the captured traces. With the aforementioned
features, SYS-HMRBT supports a diverse range of design/debugging/
monitoring activities, including module development,
chip integration, hardware/software integration and debugging,
system behavior monitoring, system performance/power analysis
and optimization, etc. The users are allowed to tradeoff
between trace granularity and trace depth in order to make the
most use of the on-chip trace memory or I/O pins.