09-05-2012, 04:15 PM
An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform
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INTRODUCTION
FIR filters are employed in the majority digital signal
processing (DSP) based electronic systems. The emergence of
demanding applications (software defined radio, image,
audio/video processing and coding, sensor filtering, etc.) in
terms of power, speed, performance, system compatibility and
reusability make it imperative to design the reconfigurable
architectures. Moreover, in case of aerospace application, there
is the added concern for fault-tolerant FIR filtering fabrics,
which are capable to respond to various malfunctions caused
by endogenous or exogenous factors.
PARTIAL RECONFIGURATION DESIGN FLOW
Many researchers have been proposed many partial
reconfiguration methods (JBits, PARBIT, etc) [1][2]. But these
methods are difficult to apply real applications because these
methods reconfigure the gate-level based. Module based partial
reconfiguration method was proposed by Xilinx and can
reconfigure the system-level based [3][4]. Recently, more
flexible partial reconfiguration method was suggested. There
are two major features in new partial reconfiguration design
platform. One is that Xilinx Virtex-4 FPGAs, which are most
popular FPGAs in these days, support the partial
reconfiguration design using slice-based bus macro.
RECONFIGURABLE FIR FILTER DESIGN
The FIR filter computes an output from a set of input
samples, which is multiplied by a set of coefficients. And then
the FIR filter adds together to produce the output as shown in
Fig 4. Implementation of FIR filters can be undertaken in either
hardware or software [6]. A software implementation will
require sequential execution of the filter functions. Hardware
implementation of FIR filters allows the filter functions to be
executed in a parallel manner, which makes improved filter
processing speed as fast as possible but is less flexible for
changes. Thus, reconfigurable FIR filter offers both the
flexibility of computer software, and the ability to construct
custom high performance computing circuits.
CONCLUSION
In this paper, we present a reconfigurable FIR filter design
using dynamic partial reconfiguration, which has area
efficiency, flexibility and configuration time advantage
allowing dynamically inserting and/or removing the partial
modules. The proposed method produces a reduction in
hardware cost and allows performing partial reconfiguration,
where a reduced bit-stream reconfigures only a given subset of
internal components. In the future, self-reconfigurable
hardware platform using microcontroller unit and configuration
memory will be promising solution for automatic partial
reconfiguration of digital circuit in the run-time environment.