28-12-2012, 02:57 PM
Architecture of FPGAs and CPLDs: A Tutorial
1Architecture of FPGAs.pdf (Size: 216.36 KB / Downloads: 20)
Abstract
This paper provides a tutorial survey of architectures of commercially available high-capacity
field-programmable devices (FPDs). We first define the relevant terminology in the field and then
describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple
PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We
then give details of the architectures of all of the most important commercially available chips,
and give examples of applications of each type of device
Introduction to High-Capacity FPDs
Prompted by the development of new types of sophisticated field-programmable devices (FPDs),
the process of designing digital hardware has changed dramatically over the past few years.
Unlike previous generations of technology, in which board-level designs included large numbers
of SSI chips containing basic gates, virtually every digital design produced today consists mostly
of high-density devices. This applies not only to custom devices like processors and memory, but
also for logic circuits such as state machine controllers, counters, registers, and decoders. When
such circuits are destined for high-volume systems they have been integrated into high-density
gate arrays. However, gate array NRE costs often are too expensive and gate arrays take too long
to manufacture to be viable for prototyping or other low-volume scenarios. For these reasons,
most prototypes, and also many production designs are now built using FPDs. The most compelling
advantages of FPDs are instant manufacturing turnaround, low start-up costs, low financial
risk and (since programming is done by the end user) ease of design changes.
The market for FPDs has grown dramatically over the past decade to the point where there is
now a wide assortment of devices to choose from. A designer today faces a daunting task to
research the different types of chips, understand what they can best be used for, choose a particular
manufacturers’s product, learn the intricacies of vendor-specific software and then design the
hardware. Confusion for designers is exacerbated by not only the sheer number of FPDs available,
but also by the complexity of the more sophisticated devices. The purpose of this paper is to
provide an overview of the architecture of the various types of FPDs. The emphasis is on devices
with relatively high logic capacity; all of the most important commercial products are discussed.
Definitions of Relevant Terminology
The most important terminology used in this paper is defined below.
• Field-Programmable Device (FPD) — a general term that refers to any type of integrated circuit
used for implementing digital hardware, where the chip can be configured by the end user
to realize different designs. Programming of such a device often involves placing the chip into
a special programming unit, but some chips can also be configured “in-system”. Another name
for FPDs is programmable logic devices (PLDs); although PLDs encompass the same types of
chips as FPDs, we prefer the term FPD because historically the word PLD has referred to relatively
simple types of devices.
• PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels
of logic, an AND-plane and an OR-plane, where both levels are programmable (note: although
PLA structures are sometimes embedded into full-custom chips, we refer here only to those
PLAs that are provided as separate integrated circuits and are user-programmable).
Evolution of Programmable Logic Devices
The first type of user-programmable chip that could implement logic circuits was the Programmable
Read-Only Memory (PROM), in which address lines can be used as logic circuit inputs and
data lines as outputs. Logic functions, however, rarely require more than a few product terms, and
a PROM contains a full decoder for its address inputs. PROMS are thus an inefficient architecture
for realizing logic circuits, and so are rarely used in practice for that purpose. The first device
developed later specifically for implementing logic circuits was the Field-Programmable Logic
Array (FPLA), or simply PLA for short.
User-Programmable Switch Technologies
The first type of user-programmable switch developed was the fuse used in PLAs. Although fuses
are still used in some smaller devices, we will not discuss them here because they are quickly
being replaced by newer technology. For higher density devices, where CMOS dominates the IC
industry, different approaches to implementing programmable switches have been developed. For
CPLDs the main switch technologies (in commercial products) are floating gate transistors like those used in EPROM and EEPROM, and for FPGAs they are SRAM and antifuse. Each of these
is briefly discussed below.
An EEPROM or EPROM transistor is used as a programmable switch for CPLDs (and also
for many SPLDs) by placing the transistor between two wires in a way that facilitates implementation
of wired-AND functions. This is illustrated in Figure 4, which shows EPROM transistors as
they might be connected in an AND-plane of a CPLD. An input to the AND-plane can drive a
product wire to logic level ‘0’ through an EPROM transistor, if that input is part of the corresponding
product term. For inputs that are not involved for a product term, the appropriate
EPROM transistors are programmed to be permanently turned off. A diagram for an EEPROMbased
device would look similar.
Although there is no technical reason why EPROM or EEPROM could not be applied to
FPGAs, current commercial FPGA products are based either on SRAM or antifuse technologies,
as discussed below.
Computer Aided Design (CAD) Flow for FPDs
When designing circuits for implementation in FPDs, it is essential to employ Computer-Aided
Design (CAD) programs. Such software tools are discussed briefly in this section to provide a feel
for the design process involved.
CAD tools are important not only for complex devices like CPLDs and FPGAs, but also for
SPLDs. A typical CAD system for SPLDs would include software for the following tasks: initial
design entry, logic optimization, device fitting, simulation, and configuration. This design flow is
illustrated in Figure 7, which also indicates how some stages feed back to others. Design entry
may be done either by creating a schematic diagram with a graphical CAD tool, by using a textbased
system to describe a design in a simple hardware description language, or with a mixture of
design entry methods. Since initial logic entry is not usually in an optimized form, algorithms are
employed to optimize the circuits, after which additional algorithms analyse the resulting logic
equations and “fit” them into the SPLD. Simulation is used to verify correct operation, and the
user would return to the design entry step to fix errors. When a design simulates correctly it can be
loaded into a programming unit and used to configure an SPLD. One final detail to note about Figure
7 is that while the original design entry step is performed manually by the designer, all other
steps are carried out automatically by most CAD systems.