06-05-2013, 03:24 PM
Area-Saving Technique for Low-Error Redundant Binary Fixed-Width Multiplier Implementation
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Abstract
A recently proposed architecture of redundant
binary fixed-width multiplier was shown to outperform several
normal binary fixed-width multipliers in terms of accuracy.
However, its merit due to the carry-free addition property of the
binary signed digit (BSD) partial products has been offset by the
high area overhead of the redundant binary full adder tree. To
achieve low–error fixed-width multiplication with smaller silicon
area, we propose a hybrid structure which makes use of dual
polarity high order column compressors and (3:2) counters to
parallelly reduce the positive and negative BSD partial products.
INTRODUCTION
Fixed-width multipliers [1-13] are widely used in
application specific data paths in multimedia and wireless
communication applications where some degree of saturation
error within the dynamic range of interest is tolerable
depending on the level of perceptual quality and signal-tonoise
degradation it induced. For maximal area reduction, the
least significant half of the partial products are truncated to
produce a final product with reduced precision. To achieve a
lower average error and narrower error spread for all
legitimate operands within the dynamic range, errorcompensation
circuitry with area overhead much lower than
the truncated part is introduced.
In [1-3], a constant error compensation technique is used to
compensate for the truncation errors without considering the
bit-width of the inputs. Although these methods are attractive
in terms of their hardware simplicity, they introduce large
average and mean square errors compared to those techniques
that use adaptive error compensation [4-13]. Adaptive error
compensation techniques estimate the error compensation
values (ECV) from a few most significantly weighted bits of
the truncated part of the partial products. Fixed-width
multipliers can be categorized in the similar way as their fullwidth
counterparts.
EXPERIMATAL RESULTS
The proposed low-error redundant binary n×n-bit fixedwidth
multipliers are implemented for n = 8, 10 and 12 and
synthesized by Synopsys Design Compiler using the TSMC
0.18 μm CMOS standard cell library. To demonstrate the
effectiveness of the proposed area-saving technique, the
designs are compared with the most recent low cost carry-free
fixed-width multipliers [10] of the same statistical error
performance in Table II. Both designs are area optimized by
the same synthesis tool with the same timing constraints of 3.6
ns to 4.0 ns.
CONCLUSIONS
This paper proposes an area-saving technique to reduce
its high area cost in the summation of partial products. The
proposed carry-saved addition of the BSD partial products
consists of three stages and involves a mixture of high-order
column compressors and (3:2) counters. While maintianing the
low average error and error variance of the original fixedwidth
multiplier, around 40% of precious silicon premium can
be saved from a 10×10-bit fixed-width multiplication.