22-10-2012, 05:09 PM
Asynchronous chip
Asynchronous-Chips.pdf (Size: 175.49 KB / Downloads: 19)
INTRODUCTION
Computer chips of today are synchronous. They contain a main clock,
which controls the timing of the entire chips. There are problems, however,
involved with these clocked designs that are common today.
One problem is speed. A chip can only work as fast as its slowest
component. Therefore, if one part of the chip is especially slow, the other
parts of the chip are forced to sit idle. This wasted computed time is
obviously detrimental to the speed of the chip.
New problems with speeding up a clocked chip are just around the
corner. Clock frequencies are getting so fast that signals can barely cross the
chip in one clock cycle. When we get to the point where the clock cannot
drive the entire chip, we’ll be forced to come up with a solution. One
possible solution is a second clock, but this will incur overhead and power
consumption, so this is a poor solution. It is also important to note that
doubling the frequency of the clock does not double the chip speed,
therefore blindly trying to increase chip speed by increasing frequency
without considering other options is foolish.
The other major problem with c clocked design is power consumption.
The clock consumes more power that any other component of the chip. The
most disturbing thing about this is that the clock serves no direct
computational use. A clock does not perform operations on information; it
simply orchestrates the computational parts of the computer.
New problems with power consumption are arising. As the number of
transistors on a chi increases, so does the power used by the clock.
Therefore, as we design more complicated chips, power consumption
becomes an even more crucial topic. Mobile electronics are the target for
many chips.
DISCUSSION
Asynchronous, or clock less, design has advantages over the
synchronous design.
The first of these advantages is speed. Chips can run at the average
speed of all its components instead of the speed of its slowest component, as
was the case with a clocked design. Also the need to have a clock running at
a speed such that the signal can reach all parts of the chip is eliminated.
Therefore, the speed of an asynchronous design is not limited by the size of
the chip.
An example of how much an asynchronous design can improve speed
is the asynchronous Pentium designed by Intel in 1997 that runs three times
as fast as the synchronous equivalent. This speedup is certainly significant
and proves the usefulness of a clock less design.
ASYNCHRONOUS LOGIC
Data-driven circuits design technique where, instead of the
components sharing a common clock and exchanging data on clock edges,
data is passed on as soon as it is available. This removes the need to
distribute a common clock signal throughout the circuit with acceptable
clock skew. It also helps to reduce power dissipation in CMOS circuits
because gates only switch when they are doing useful work rather than on
every clock edge.
There are many kinds of asynchronous logic. Data signals may use
either “dual rail encoding” or “data building”. Each dual rail encoded
Boolean is implemented as two wires. This allows the value and the timing
information to be communicated for each data bit. Bundled data has one
wire for each data bit and another for timing. Level sensitive circuits
typically represent a logic one by a high voltage and a logic zero by a low
voltage whereas transition signaling uses a change in the signal level to
convey information. A speed independent design is tolerant to variations in
gate speeds but not to propagation delays in wires; a delay insensitive
circuit is tolerant to variations in wire delays as well.
How fast is your personal computer?
When people ask this question, they are typically referring to the
frequency of a minuscule clock inside the computer, a crystal oscillator that
sets the basic rhythm used throughout the machine. In a computer with a
speed of one Gigahertz, for example, the crystal “ticks” a billion times a
second. Every action of he computer takes place in tiny step; complex
calculations may take many steps. All operations, however, must begin and
end according to the clock’s timing signals.