30-04-2012, 12:24 PM
Architecting, Designing, Implementing, and Verifying Low-Power Digital
Integrated Circuits
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Introduction
In recent years, power consumption has moved to the forefront of digital integrated circuit (IC)
development
concerns. The combination of higher clock speeds, greater functional integration, and
smaller process geometries has contributed to significant growth in power density. Furthermore, with
every new process generation, leakage power consumption increases at an exponential rate.
It is common to think of low-power designs only in the context of handheld, battery-powered devices
such as personal digital assistants (PDAs) and cell phones. And it is certainly fair to say that this class
of device is at the top of low-power development concerns. In reality, however, power consumption
(and corresponding heat generation) is also of significant interest to semiconductor segments with
fixed installations, such as networking, set-top boxes, and computing devices. For example, the
InformationWeek “Power Surge” article on 27 February 2006 reported that data center electricity
costs are now in the range of US $3.3 billion annually, and it can cost more to cool a data center than
it does to lease the floor space in which to house it. Additionally, consumers increasingly demand
quieter
devices for their living rooms and desktops, and low-power designs help manufacturers
eliminate
noisy cooling fans from set-top boxes and other products.
Power Architecture
Following the definition of the chip/system architectural specification, the next step in the development
process is to refine the power architecture. For example, the architectural specification may specify that
a certain block should be implemented in such a way that it is capable of being completely powered
down. In the power architecture portion of the process, the team will determine just how often this
block is to be shut down, and also any interdependencies among this block and other blocks and modes.
To place this in perspective, before a certain block is powered down, it may be necessary to first power
down one or more other blocks in a specific order, and to ensure that each block is completely powered
down before a subsequent block is powered down. Similarly, when this portion of the design is restored
to its operating condition, it will be necessary to ensure that the various blocks are powered up in a
specific order.
Power -Aware Design
In this context, “design” refers to the portion of the flow where—taking the results from the power
architecture phase—the design engineers capture the RTL descriptions for the various blocks forming
the design. The designers associated with each block are responsible for ensuring that block will meet
its functional, timing, and power requirements while using the minimum silicon real estate.
This means the designers need to know the target voltage level(s) for their block so that they can
understand the various timing and power challenges. If the system as a whole employs multiple voltage
levels, level shifters must be inserted between domains, and the designers must know if these are present
in their timing paths because these cells could result in significant cell delays.
Designers need the ability to quickly and easily explore and evaluate alternative micro-architectures,
such as unraveling loops, resource sharing, varying the number of pipeline stages (more stages result
in higher performance at the expense of increased power consumption, area utilization, and latency),
using hardware accelerator(s) versus microcode, and so forth. With regard to power-centric design, this
involves the ability to capture toggle values to gain an accurate estimation of power—first with the RTL
representations and later at the gate level.