25-07-2012, 04:43 PM
BASICS OF DIGITAL CMOS DESIGN
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INTRODUCTION
The Combinational logic circuits, or gates, perform Boolean operations on multiple input
variables and determine the outputs as Boolean functions of the inputs. Logic circuits can be
represented as a multiple-input, single-output system is shown in
The Combinational logic circuits are the basic building blocks of all digital systems.
All input variables are represented by node voltages, referenced to the ground potential. The
output node is loaded with a capacitance Cload which represents the combined parasitic device
capacitance in the circuit and the interconnect capacitance components. Static & dynamic
characteristics of various combinational MOS logic circuits will be described in this chapter.
nMOS LOGIC CIRCUITS WITH A MOS LOADS
Two-Input NOR Gate
The circuit diagram, the logic symbol, and the corresponding truth table of the two-input
depletion-load NOR gate is shown in figure 1.2.
A two-input depletion-load NOR gate, its logic symbol, and truth table.
The Boolean OR operation is performed by parallel connection of the two
enhancement-type nMOS driver transistors. If the input voltage VA or VB is equal to logichigh
level, the corresponding driver transistor turns on and provides a conducting path
between the output node and the ground, the output voltages becomes low. When VA =
VOL, VB = VOH or VA = VOH, VB = VOL, the NOR2 circuit reduces to nMOS depletionload
inverter. The output low voltage level VOL in both cases is given by
When VA = VB = VOH, two parallel conducting paths are created between the output node
and the ground, then VOL is given by
When VA = VB = VOL, both driver transistors remain cut-off, the output node voltage is
pulled to a logic-high level by depletion-type nMOS load transistor.
Generalized NOR Structure with Multiple Inputs
An n-input NOR with nMOS depletion load logic and equivalent circuit are shown in figure
The combined current ID in the circuit is supplied by the driver transistors which are
Generalized n-input NOR Structure and equivalent inverter circuit.
The combined pull-down current is expressed as
The multiple-input NOR gate can also be reduced to an equivalent inverter shown in figure
The source terminals of all enhancement-type nMOS driver transistors are connected
to ground, and the drivers do not experience any substrate-bias effect. The depletion-type
nMOS load transistor is subjected to substrate-bias effect.
Transient Analysis of NOR2 Gate
The figure 1.4 shows the two-input NOR gate with all of its relevant parasitic device
capacitance. The parasitic capacitances are combined into one lumped capacitance,
connected between the output node and the ground.