22-03-2012, 03:34 PM
Energy Recovery VLSI
Seminar_Papaefthymiou_140307.pdf (Size: 1.31 MB / Downloads: 101)
Conventional CMOS Operation
● Constant supply voltage Vdd
● One-way street to ground
● High voltage drops across conducting devices
● Energy dissipation grows with CV2
Charge Recovery Operation
● Time-varying “power-clock” Vpc
● Charge recovered from load C
● Charge transfer through R in time T
● Energy dissipation grows with (RC/T) CV2
– Reducing R decreases dissipation
– Increasing T decreases dissipation
The Key Questions
1. Which capacitance to recover from?
− Clock network? Gates? Bit lines? I/O? Other?
− Balancing? Other issues?
2. How to store/reuse recovered energy?
− Capacitors? Inductors?
− How many power-clock phases?
3. What circuits do the recovery?
− Power-clock generator design
Quick Glance at History
● Physics (1970s)
– Logical reversibility of computation
– Connection to thermodynamics (“adiabatic” computing)
– No absolute minimum to energy dissipation, if computing
is arbitrarily slow. (Does not have to be slow, however.)
● Engineering (1990s)
– Logic circuitry
– Energy recycling circuitry
– VLSI prototyping