10-08-2012, 04:43 PM
Verilog DMA Controller IP Core
DMA100_brochure[1].pdf (Size: 183.9 KB / Downloads: 92)
INTRODUCTION
The DMAC100 is used to transfer large amounts of
data between memories and peripherals using AHB/
AXI buses in SoC environment in order to reduce
CPU overhead for data transfers.
The DMAC100 has one Bus Slave interface for programming
its internal registers and one or two bus
master interfaces for data transfer.
The DMAC100 has parameterized number of channels,
each channel transfers data between one or
two slaves (memory or peripheral). The direction,
bus master, data width, transfer size, burst size and
endiannity are configurable.
Each bus master interface has its own channels requests
arbiter. The arbitration scheme is programmable
and can be fixed priority arbitration or round
robin arbitration.
The DMAC100 supports double buffered operation
using two read-in write-out 64bits wide FIFOs. Each
bus master interface has bidirectional access to
each FIFO to achieve best system bus.
The DMAC100 supports a parameterized number of
DMA peripheral requestors which can be routed to
each one of the DMAC100 channels.
An individually maskable interrupt is generated for
transfer complete, time out and error. All channels
interrupts are stored in status registers and can be
accessed before and after masking.
All DMAC100 channels perform Scatter/gather operation
through linked list Items (LLI). The first LLI is
programmed into each DMAC channel.
The DMAC100 has single clock domain architecture.
PROGRAMMABLE OPTIONS
• DMA enable/disable
• DMA interrupts masking option
• DMA arbitration type
• DMA master selection for source and destination
• DMA masters Endiannity
• Channel’s enable/disable
• Channel’s source and destination addresses
• Channel’s source and destination address access
mode
• Channel’s data transfer direction
• Channel’s transfer (message) size in bytes
• Channel’s maximal burst size in bytes
• Channel’s maximal data width
• Channel’s LLI first address
• Channel’s interrupts enable/disable