06-07-2012, 10:17 AM
Bit Level Arithmetic Architectures
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Parallel Multipliers with Modified Booth Recoding :
Reduces the number of partial products to accelerate the
multiplication process.
The algorithm is based on the fact that fewer partial
products need to be generated for groups of consecutive
zeros and ones. For a group of “m” consecutive ones in the
multiplier, i.e.,
…0{11…1}0… = …1{00…0}0… - …0{00…1}0…
= …1{00…1}0…
instead of “m” partial products, only 2 partial products
need to be generated is signed digit representation is
used.
Ø Hence, in this multiplication scheme, the multiplier bits
are first recoded into signed-digit representation with
fewer number of nonzero digits; the partial products are
then generated using the recoded multiplier digits and
accumulated.
Bit-Serial FIR Filter
Bit-level pipelined bit-serial FIR filter, y(n) = (-7/8)x(n) + (1/2)x(n-1),
where constant coefficient multiplications are implemented
as shifts and adds as y(n) = -x(n) + x(n)2-3 + x(n-1)2-1.
(a)Filter architecture with scaling operators;
(b) feasible bit-level pipelined architecture
Canonic Signed Digit Arithmetic
• Encoding a binary number such that it contains the
fewest number of non-zero bits is called canonic
signed digit(CSD).
• The following are the properties of CSD numbers:
Ø No 2 consecutive bits in a CSD number are non-zero.
Ø The CSD representation of a number contains the
minimum possible number of non-zero bits, thus the name
canonic.
Ø The CSD representation of a number is unique.
Ø CSD numbers cover the range (-4/3,4/3), out of which
the values in the range [-1,1) are of greatest interest.
Ø Among the W-bit CSD numbers in the range [-1,1), the
average number of non-zero bits is W/3 + 1/9 + O(2-W).
Hence, on average, CSD numbers contains about 33%
fewer non-zero bits than two’s complement numbers.