15-01-2013, 12:01 PM
FPGA Implementation of CIS Speech Processing Strategy for Cochlear Implants
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Abstract
Continuous Interleaved Sampling (CIS) is one of the
most famous speech processing approaches used in Cochlear
Implants speech processors. In the future, to meet the need of
totally implantable cochlear implants (TICI), the power
consumption needs to be reduced. A CIS application specified
integrated circuit (ASIC) has an obvious dissipation advantage
compared with a DSP-based circuit. In order to design an ASIC,
it is necessary to make a verification of its feasibility. A lot of
papers have showed their verification work in software
simulation. But this paper proposes a hardware-level CIS model
working at 1MHz which can be implemented on a FPGA chip. A
preliminary report containing resource occupation of the circuit
scale is produced in the end. It gives us a better guidance for the
design of a CIS ASIC in the next step.
INTRODUCTION
Cochlear Implant (CI) is an electronic device that can be
implanted into the inner ear of profoundly deaf patients to help
restore their hearing. All CI systems at present are designed
into two main parts: an external unit and an internal unit [1].
The former unit, known as the speech processor consists of a
DSP unit, a power amplifier, and a Radio Frequency (RF)
transmitter. It is in charge of converting the sound signal into a
stream of bits that can be transmitted by the RF link. The latter
unit consists of a RF receiver and a stimulator. The stimulator
decodes the RF bit stream and converts it into electric currents
to be delivered to corresponding electrodes [2]. Actually, CI is
a functional replacement of the biological sensory hair cells in
the cochlea. It bypasses the normal hearing mechanism and
stimulates auditory neurons directly.
Procedure of Modeling
Figure 2 is a partial view of the total framework of a 14-
channel CIS model. First of all, a "From Wave file" reads a
audio file with output in frames which is a n × 1 matrix.
Secondly, after passing through an "Unbuffer" module
serializing the data, the audio data is sent to CIS flow to deal
with. The "Gateway In" module, which converts data types in
Simulink, such as integer, double and fixed-point, into fixedpoint
type accepted by System Generator, is the only interface
connecting Simulink and System Generator.
SYNTHESIS REPORT AND SIMULATION RESULTS
As shown in table Ⅰ, a 457-order parallel filter takes up
56% resource of the FPGA chip, however, that percentage of a
serial filter is only 2.4%. Clearly, choosing serial filter makes it
possible to put more channels into the chip.
The scale of the 14-channel circuit is about 1.25 Million
gates according to the slice occupation in Table Ⅱ. Overall, the
two filter-module's occupation is 84% of that of a channel. For
14 channels, DSP48As is the bottleneck to limit the number of
channels putting into a chip.
CONCLUSION AND FUTURE WORK
The procedure of modeling CIS strategy and
implementation on Xilinx 1800A FPGA chip is provided here
in detail. To accommodate more channels in one FPGA chip,
Serial FIR filter is chosen because of less resource occupation
than parallel FIR filter. To make it easier and faster to compute
xp for hardware, line approximation algorithm is adopted. An
initial circuit scale report is produced by using the combination
of System Generator, Simulink and ISE Design Suite. The
simulation result proves the feasibility of FPGA
implementation for CIS strategy. Although the circuit scale
seems very large, the low working frequency (1MHz) brings us
a huge advantage to design low-power ASIC of CIS in the
future.