07-12-2012, 01:35 PM
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques
Braun’s Multiplier.PDF (Size: 617.41 KB / Downloads: 81)
Abstract:
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should
be proved and then it would be optimized before implementation. Multiplication which is the basic building
block for several DSP processors, Image processing and many other. The Braun multipliers can easily be
implemented using Field Programmable Gate Array (FPGA) devices. This research presented the
comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The
implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are
proposing that adder block which we implemented our design (fast addition) and we compared the results
of that so that our proposed method is effective when compare to the conventional design. There is the
reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified
using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance
as compared to Spartan-3E and Virtex-4 FPGA devices.
INTRODUCTION
Multiplication – an important fundamental function in arithmetic operation. Currently
implemented in many DSP applications such as FFT, Filtering etc., and usually contribute
significantly to time delay and take up a great deal of silicon area in DSP system. Now – a – days
time is still an important issue for the determination of the instruction cycle time of the DSP chip.
Both the multiplication and the DSP play a vital role in the implementation of VLSI system.
Multiplication – Repeated addition of n – bits will give the solution for the multiplication. ie.
Multi-operand addition process. The multi – operand addition process needs two n – bit operands.
It can be realized in n- cycles of shifting and adding. This can be performed by using parallel or
serial methods. This will be simple to implement in two’s complement representation, since they
are independent of the signs. It is advantageous to exploit other number systems to improve speed
and reduce the chip area and power consumption.
PROPOSED METHOD:
The Braun’s Multiplier (fig. 1) which uses the full adder block adding the PP. in the proposed
method we have used the fast addition [9] method so that we are reducing the number of slices,
LUTs, and the delay is getting reduced. The fig. 4 which shows the proposed method of the
Braun’s multiplier.
In the proposed method the number of LUTs, slices are reduced and mainly the delay has been
very less when compare to the conventional method. The table.1 will give the comparison result
of the all the methods which is simulated and synthesized and tested in the FPGA boards.
The Row bypassing and the Column bypassing method also simulated and synthesized by using
the proposed method. Table 1 will show the result of those multipliers.
CONCLUSION
In this paper we have presented the hardware implementation of the Multipliers in the FPGA
devices using Verilog HDL. The design was implemented on the Xilinx Spartan – 3E (xc3s500e-
4ft256), Virtex – 4 (xc4vlx15-10-sf363), Virtex – 5 (xc5vlx30-1-ff324), and Virtex – 6
((xc6vlx75tl-1L-ff484) FPGAs. The proposed Multiplier shows that reduced utilization when
compare to all other multipliers. The average pin delay and combinational path delay has been
reduced in the Virtex – 6 Low power FPGA device. So the Virtex – 6 Low power is obtained the
best result when compare to the other FPGA devices. And it is feasible for the DSP Processor,
Image processing and multimedia technology.