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ABSTRACT
Built-in self-test for logic circuits or logic BIST, is an effective solution for the test cost, test quality, and test reuse problems. Logic BIST implements most ATE functions on chip so that the test cost can be reduced through less test time, less tester memory requirement, or a cheaper tester. Logic BIST applies a large number of test patterns so that more defects, either modeled or un-modeled, can be detected. IN addition, logic BIST makes it easy to conduct the at-speed test for detecting timing-related defects. Furthermore, a BISTedcore makes SoC testing easier. Most of logic BIST schemes are based on the STUMPS structure, which applies random patterns generated by a PRPG to a full-scan circuit in parallel and compresses the responses into a signature with a MISR. This signature is compared with Golden signature to check test pass/fail information and defect or not. Expected output includes the Designed STUMP Based Architecture, Which is Test per Scan Using Verilog HDL and Simulation Result having information of design is defect free or not.
Hardware Test Pattern Generator: •This module generates the test patterns required to sensitize the faults and propagate the effect to the outputs • As the test pattern generator is a circuit (not equipment) its area is limited. •So storing and then generating test patterns obtained by ATPG algorithms on the CUT (discussed in Module XI) using the hardware test pattern generator is not feasible. •Instead, the test pattern generator is basically a type of register which generates random patterns which act as test patterns. The main emphasis of the register design is to have low area yet generate as many different patterns (from 0 to 2 n -1, if there are n flip-flops in the register) as possible.
In computing, a linear-feedback shift register (LFSR) is a shift registerwhose input bit is a linear function of its previous state.
The most commonly used linear function of single bits is exclusive-or(XOR). Thus, an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register value.
The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.
For generating data encryption keys, random numbers are very much useful in the various applications such as communication channel, bank security, etc. it is used to design encoder and decoder for sending and receiving data in noisy communication channel. They have also been used aesthetically, for example in literature and music, and are of course ever popular for games and gambling. Applications of LFSRs also include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences.
BIST is used to make faster, less-expensive integrated circuits manufacturing tests. The IC has a function that verifies all or a portion of the internal functionality of the IC. In some cases, this is valuable to customers, as well. For example, a BIST mechanism is provided in advanced fieldbus systems to verify functionality. At a high level this can be viewed similar to the PC BIOS’s power-on self-test (POST) that performs a self-test of the RAM and buses on power-up.
LFSRs are used in circuit testing, for test-pattern generation (for exhaustive testing, pseudo-random testing or pseudo-exhaustive testing) and for signature analysis.