22-10-2012, 01:33 PM
Design of a Digital FM Demodulator based on a 2ndº Order All-Digital Phase-Locked Loop
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ABSTRACT
A software-defined radio (SDR) is a wireless communication
device in which all of the signal processing is implemented in
software. By simply downloading a new program, a SDR is able
to interoperate with different wireless protocols, incorporate new
services, and upgrade to new standards. Therefore, FPGAs have
been used extensively for implementing essential functions in
SDR architectures. In this paper, we explore the design of a
Digital FM Receiver using the approach of an All-Digital Phase
Locked-Loop (ADPLL). The digital FM Receiver circuit is
designed using pure VHDL, then simulated and synthesized using
ModelSim SE 6 and LeonardoSpectrum Level 3, respectively.
The final circuit operates at a frequency up to 150MHz and
occupies the area around 15K logic gates.
INTRODUCTION
Digital receivers revolutionized electronic systems providing
innumerable applications and functionalities. Communications,
transmission data, signal processing and many other areas have
benefited and undergone a true revolution due to these devices.
Therefore, the use of reprogrammable radio architectures leads us
to the concept of Software-Defined Radios (SDR) [1]. This means
that communication terminals can support a wide range of
frequencies and demodulate various transmission standards.
However, the design flow and circuit techniques of contemporary
transceivers for Multi-GHz mobile RF wireless applications are
typically analog intensive and utilize process technologies that are
more complex than or incompatible with standard digital CMOS
process. Thus, Field Programmable Gate Arrays (FPGAs) are an
attractive option to perform many of these SDR functions for
reasons of cost, performance, and programmability [2-3].
Furthermore, since SDR functions are commonly based on
hardware reconfiguration, VHDL can be used as the
“programming language” in the development and implementation
of high speed digital signal processing algorithms within the
FPGAs [4]. Nevertheless, one should acknowledge the efforts that
ensure that in order to achieve the flexibility required by modern
SDR's, it should be performed by combining a DSP processor
(reconfigurable software) and an FPGA (reconfigurable hardware)
[5].
RELATED WORK
Frequency modulation has been in ubiquitous use for
communication media such as radio broadcast FM, TV audio,
VHS HiFi, laser disc, and even digital wireless in the form of
frequency shift keying FSK. Many efforts have been made to
integrate an FM receiver on a single chip using various
architectures, but the performance has been limited by the analog
signal-processing accuracy [6-8]. The main issue of integrating an
FM demodulator on a chip is how to accurately discriminate a
small frequency deviation of the FM signal from its center
frequency. Most FM demodulators use either the Foster–Seeley
method or phase-locked loops (PLL). The PLL behaves as a
narrow-band tracking filter, with its loop-filter output exhibiting a
frequency discriminating characteristic. It is readily
implementable in integrated forms, but the linearity of the
voltage-controlled oscillator VCO affects the overall linearity [9].
Hence, Digital PLL’s can overcome some of the weaknesses of
analog PLL’s. Also, the digital tangent method can compute
frequency from the ratio of in-phase and quadrature (I–Q) signals
[10-11]. These digital methods for wide dynamic range IF
processing and accurate frequency discrimination require either
extensive numerical processing or large read-only memory
(ROM) lookup tables. In this work, a highly linear digital FM
demodulator is proposed. The circuit has as main core an All-
Digital Phase-Locked Loop (ADPLL) described in VHDL
language.
Simulations
The system clock frequency and the sampling frequency are
16MHz. FM modulation is ±10KHz at a 1MHz center frequency.
The modulation is just +-1.0% of the 1MHz carrier frequency. In
the simulation, we set the sampling frequency to 16MHz.
However, we can scale the sampling frequency as needed. Fig. 7
shows the simulation waveform for all digital FM receiver circuit
subjected to square wave modulated data, while Fig. 8 shows the
simulation waveform for All Digital FM Receiver circuit
subjected to triangular wave modulated data. The first row shows
the FM modulated waveform according to the sending data. The
second row is the NCO output and the third row is the phase
detector (multiplier) output. The fourth row and the fifth row are
the accumulator output and the demodulated output, respectively.
At the initial simulation phase, the demodulated output overshoots
since the phase synchronization is in convergence phase and then
system is stable. From Fig. 7 and Fig. 8, designed FM receiver
circuit successfully demodulates input signal back to the original
signal.
CONCLUSIONS
The output of the phase detector and loop filter gives us a clear
vision on how both circuits develop their function on the FM
demodulator. As we have shown, the output signal of the ADPLL
is already the required output signal, albeit only a FIR filtering is
necessary at the final stage. With this work we demonstrated that
it is possible to implement digitally and in a simple form an FM
demodulator circuit. About 14,000 logic gates for processing the
demodulation are needed. Therefore, the fine tune of each filter
demonstrates that the reprogrammability allows us to modify
parameters without the direct hardware interaction. And this is
undoubtedly the main constraint in SDR systems.