27-07-2012, 09:34 AM
CMOS Current Mode Logic Gates for High-Speed Applications
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Abstract
This paper presents results of a design that uses
CMOS current mode logic that can be used to implement the high
precision, speed critical elements of the mixed-signal systems. The
design is based upon the 0.25-μm CMOS TSMC process. The
propagation delays of the new current mode logic are compared
to those of equivalent gates implemented in conventional CMOS
logic. The results show a propagation delay improvement of more
than 200% using the current mode logic. The application of the
proposed current mode building blocks is illustrated in a typical
mixed-signal circuit, the phase detector for a high-speed phase
locked loop with good speed improvement over conventional
CMOS logic.
INTRODUCTION
Conventional pull-up PMOS, pull-down NMOS static logic
is popular because of its convenient availability in standard
library cells, small area usage, low power dissipation, and high
noise margins [1]. Even though the static power consumption
of the conventional CMOS logic gate is zero ideally, it
dynamically generates a large current pulse flowing from the
power supply to the ground during the state transition. The
coupling of the high switching spike noise may cause cross
talk between the analog and the digital circuitry. Even worse,
the switching noise might induce latch up which can possibly
destroy devices with the integrated circuit due to overheating
[2], [3].
SIMULATION COMPARISON
The performance of a PLL system is ultimately determined
by the ability of the phase detector to respond to incoming
data with a short delay time [9]. To compare the behavior
of the phase detector built on the MCML and CMOS NOR
gates, the respective results are tabulated in Table II and
Table III. The error term ² is defined as ² = tdi−tdo
tdi
. tdi is
the input delay, representing the time delay between the two
inputs |Fref − Fvco|. tdo is the resolution width, representing
the difference between the pulse widths of the outputs Pup
and Pdn measured at the midpoint of the input swing. The
CMOS logic implementation provides a phase resolution of 1.2
degrees, while the MCML provides 0.25 degrees of resolution,
both measured at 400 MHz with the error tolerance about 10%.
With a propagation delay improvement of about 200% using
the current mode nor gate over the CMOS nor gate, the corresponding
MCML phase detector gains the resolution degree
improvement of 480% over the CMOS phase detector. Besides
the slower propation delay compared to that of MCML, the
conventional logic doesn’t have the dynamic symmetry in
NOR/AND gate because of one connection is dynamically
faster than the other connection due to the unsymmetric circuit
configuration shown in Fig. 1(a).
APPLICATION EXAMPLE
The phase detector is a key element in a phase locked loop
system. The use of the MCML gates may be used in the
implementation of a phase detector for use in a charge pump
based phase locked loop such as shown in Fig. 3 [5], [9].
An early arriving data pulse activates the Pup that increases
the frequency of the VCO input Fvco while a late arriving
data pulse activates the Pdn that decrease the frequency of
Fvco. Fig. 4 shows a gate level implementation of the phase
detector circuit of Fig. 3, where the basic building block is the
conventional NOR gate shown in Fig. 1(a) or the MCML NOR
gate shown in Fig. 1(b). As presented in Fig. 4, three cascaded
NOR gates are employed for AND function with appropriate
delay to reset the S/R latch.
CONCLUSION
The benefit of a faster logic propagation delays in speed
critical paths of mixed signal applications such as the phase detector
of a high-speed PLL is invaluable. The advantage for the
MCML phase detector is larger than just the propagation delay
advantage due to symmetry considerations. Even though additional
static power is required for the MCML (approximately
1.2 mW per gate), this can produce a substantial improvement
in performance as demonstrated in the PLL phase detector
application. The proposed gates may be easily integrated with
conventional CMOS logic with minimal interface problems.