29-06-2012, 04:30 PM
CMOS Inverter (static view)
CMOS Inverter.ppt (Size: 634.5 KB / Downloads: 28)
CMOS Properties
Full rail-to-rail swing high noise margins
Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless
Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out (albeit with degraded performance)
Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current
No direct path steady-state between power and ground no static power dissipation
Propagation delay function of load capacitance and resistance of transistors.