14-06-2013, 12:44 PM
CMOS Operational Amplifier
CMOS Operational.pdf (Size: 1.18 MB / Downloads: 341)
Introduction
In analog and mixed-signal systems, an operational amplifier (op amp) is commonly used
to amplify small signals, to add or subtract voltages, and in active filtering. It must have high
gain, low current draw (high input resistance), and should function over a variety of frequencies.
The goal of the project is to design a two-stage CMOS operational amplifier with low power
dissipation and high gain by using AMI C5N 0.6μm technology.
Architecture and Operation
The two-stage CMOS operational amplifier in this project includes four major
circuitries—a bias circuit, an input differential amplifier, a second gain stage, a compensation
circuit. The Input Differential Amplifier block forms the input of the op amp and provides a good
portion of the overall gain to improve noise and offset performance. The Second Gain Circuit
block is typically configured as a simple common-source stage so as to allow maximum output
swings. The Bias Circuit is provided to establish the proper operating point for each transistor in
its saturation region.
Circuit Design
The design in this project is a two-stage op amp with an n-channel input pair. The op amp
uses a dual-polarity power supply (Vdd and Vss) so the ac signals can swing above and below
ground and also be centered at ground. However, a negative power supply can be a problem for a
CMOS circuit due to remaining reverse bias of the source-substrate and drain-substrate p-n
junctions. To solve this problem, the substrate of the nMOS transistors should be always tied to
the most negative voltage (Vss) in the circuit. The power supply here is constrained within +3.3V
and -3.3V (Table 1). Based on the SPICE parameters of AMI C5N 0.6μm technology, the
topology was determined to achieve the specifications listed below in table 2 through the op amp
design procedure provided in the section 6.3 of CMOS Analog Circuit Design by Phillip Allen.
The hand calculation results provided the estimated parameters (such as transistor width and
length, capacitance, etc.) to make the circuit schematic (shown in figure 3) in Cadence Virtuoso
Schematic Editor and for the circuit analysis in Cadence SpectreS.
Simulation
For circuit analysis, eight different test-bench circuits were made and simulated to
examine the performance for each specifications listed above in table 2. All of the simulations
used 5pF for capacitance load and 1 MΩ for resistance load.
Frequency Response:
The open-loop gain, gain bandwidth, cut-off frequency, and phase margin were obtained
by using ac frequency sweep analysis. In the test-bench circuit (shown in figure 4), the ac voltage
source was connected to the Vin+ and Vin- of the op amp.
Slew Rate and Settling Time:
The slew rate is determined from the slope of the output waveform during the rising or fall
of the output when input is applied a 0.1V pulse voltage source with a 2μs period. The positive
slew rate is 5.53V/μs for schematic simulation and 5.54V/μs for layout extracted, and the
negative slew rate is -5.50V//μs for both simulations. The settling time is 0.25μs faster than the
proposed specification 1μs for both schematic and layout extracted simulations.
Input Common Mode Range (ICMR):
The test-bench configuration for the simulation of input common mode range (ICMR) is
shown in figure 9. The lower limit of ICMR is determined by when the transistor M5 is in its
saturation region, which is the current in M5 reaches its quiescent state. The ICMR for both
schematic and extracted layout simulations (shown in figure 10) is from -1.8V to 3.2V, which has
wider range than the proposed specification of ICMR (-1.5 ~ 2.5V).