25-04-2014, 04:51 PM
CMOS gate circuitry
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INTRODUCTION
Up until this point, our analysis of transistor logic circuits has been limited to the TTL
design paradigm, whereby bipolar transistors are used, and the general strategy of
floating inputs being equivalent to "high" (connected to Vcc) inputs -- and
correspondingly, the allowance of "open-collector" output stages -- is maintained.
This, however, is not the only way we can build logic gates.
Field-effect transistors, particularly the insulated-gate variety, may be used in the
design of gate circuits. Being voltage-controlled rather than current-controlled
devices, IGFETs tend to allow very simple circuit designs.
Notice how transistors Q1 and Q3 resemble the series-connected complementary pair
from the inverter circuit. Both are controlled by the same input signal (input A), the
upper transistor turning off and the lower transistor turning on when the input is
"high" (1), and vice versa. Notice also how transistors Q2 and Q4 are similarly
controlled by the same input signal (input B), and how they will also exhibit the same
on/off behavior for the same input logic levels. The upper transistors of both pairs (Q1
and Q2) have their source and drain terminals paralleled, while the lower transistors
(Q3 and Q4) are series-connected. What this means is that the output will go "high"
(1) if either top transistor saturates, and will go "low" (0) only if both lower
transistors saturate.