19-11-2012, 11:56 AM
Cache Memory
Cache Memory.ppt (Size: 763.5 KB / Downloads: 123)
Location
CPU
Internal
External
Capacity
Word size
The natural unit of organisation
Number of words
or Bytes
Unit of Transfer
Internal
Usually governed by data bus width
External
Usually a block which is much larger than a word
Addressable unit
Smallest location which can be uniquely addressed
Word internally
Cluster on M$ disks
Access Methods (1)
Sequential
Start at the beginning and read through in order
Access time depends on location of data and previous location
e.g. tape
Direct
Individual blocks have unique address
Access is by jumping to vicinity plus sequential search
Access time depends on location and previous location
e.g. disk
Access Methods (2)
Random
Individual addresses identify locations exactly
Access time is independent of location or previous access
e.g. RAM
Associative
Data is located by a comparison with contents of a portion of the store
Access time is independent of location or previous access
e.g. cache
Memory Hierarchy
Registers
In CPU
Internal or Main memory
May include one or more levels of cache
“RAM”
External memory
Backing store
Performance
Access time
Time between presenting the address and getting the valid data
Memory Cycle time
Time may be required for the memory to “recover” before next access
Cycle time is access + recovery
Transfer Rate
Rate at which data can be moved
Organisation
Physical arrangement of bits into words
Not always obvious
e.g. interleaved
So you want fast?
It is possible to build a computer which uses only static RAM (see later)
This would be very fast
This would need no cache
How can you cache cache?
This would cost a very large amount
Locality of Reference
During the course of the execution of a program, memory references tend to cluster
e.g. loops
Cache
Small amount of fast memory
Sits between normal main memory and CPU
May be located on CPU chip or module
Cache operation – overview
CPU requests contents of memory location
Check cache for this data
If present, get from cache (fast)
If not present, read required block from main memory to cache
Then deliver from cache to CPU
Cache includes tags to identify which block of main memory is in each cache slot
Direct Mapping
Each block of main memory maps to only one cache line
i.e. if a block is in cache, it must be in one specific place
Address is in two parts
Least Significant w bits identify unique word
Most Significant s bits specify one memory block
The MSBs are split into a cache line field r and a tag of s-r (most significant)