09-04-2013, 03:51 PM
ChipScope Pro 10.1 Software and Cores User Guide
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Introduction
ChipScope Pro Tools Overview
As the density of FPGA devices increases, so does the impracticality of attaching test
equipment probes to these devices under test. The ChipScope™ Pro tools integrate key
logic analyzer and other test and measurement hardware components with the target
design inside the following (hereinafter called supported devices): Virtex™, Virtex-E
Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E,
Spartan-3A, and Spartan-3A DSP devices (including the QPro™ variants of these families).
The tools communicate with these components and provide the designer with a robust
logic analyzer solution.
Design Flow
The tools design flow (Figure 1-2) merges easily with any standard FPGA design flow that
uses a standard HDL synthesis tool and the ISE 10.1 implementation tools.
ChipScope Pro Cores Description
ICON Core
All of the cores use the JTAG Boundary Scan port to communicate to the host computer via
a JTAG download cable. The ICON core provides a communications path between the
JTAG Boundary Scan port of the target FPGA and up to 15 ILA, IBA/OPB, IBA/PLB, VIO,
and/or ATC2 cores (as shown in Figure 1-1, page 20). For devices not of the Virtex-4 or
Virtex-5 families, the ICON core uses either the USER1 or USER2 JTAG Boundary Scan
instructions for communication via the BSCAN_VIRTEX primitive. The unused USER1 or
USER2 scan chain of the BSCAN_VIRTEX primitive can also be exported for use in your
application, if needed.
For Virtex-4 and Virtex-5 devices, the ICON core uses any one of the USER1, USER2,
USER3 or USER4 scan chains available via the BSCAN_VIRTEX primitives. In Virtex-4 and
Virtex-5 devices, it is not necessary to export unused USER scan chains because each
BSCAN_VIRTEX primitive implements a single scan chain.
Using Multiple Trigger Ports
The ability to monitor different kinds of signals and buses in the design requires the use of
multiple trigger ports. For example, if you are instrumenting an internal system bus in
your design that is made up of control, address, and data signals, then you could assign a
separate trigger port to monitor each signal group (as shown in Figure 1-3).
If you connected all of these different signals and buses to a single trigger port, you would
not be able to monitor for individual bit transitions on the CE, WE, and OE signals while
looking for the Address bus to be in a specified range. The flexibility of being able to
choose from different types of match units allows you to customize the ILA cores to your
triggering needs while keeping resource usage to a minimum.
Using Trigger and Storage Qualification Conditions
The ILA, IBA/OPB, and IBA/PLB cores implement both trigger and storage qualification
condition logic. The trigger condition is a Boolean or sequential combination of events that
is detected by match unit comparators that are attached to the trigger ports of the core. The
trigger condition is used to mark a distinct point of origin in the data capture window and
can be located at the beginning, the end, or anywhere within the data capture window.
Similarly, the storage qualification condition is also a Boolean combination of events that is
detected by match unit comparators that are subsequently attached to the trigger ports of
the core. However, the storage qualification condition differs from the trigger condition in
that it evaluates trigger port match unit events to decide whether or not to capture and
store each individual data sample. The trigger and storage qualification conditions can be
used together to define when to start the capture process and what data is captured.
ILA Trigger Output Logic
The ILA core implements a trigger output port called TRIG_OUT. The TRIG_OUT port is
the output of the trigger condition that is set up at run-time using the Analyzer. The shape
(level or pulse) and sense (active-High or active-Low) of the trigger output can also be
controlled at run-time. The latency of the TRIG_OUT port relative to the input trigger ports
is 10 clock cycles.
The TRIG_OUT port is very flexible and has many uses. You can connect the TRIG_OUT
port to a device pin in order to trigger external test equipment such as oscilloscopes and
logic analyzers. Connecting the TRIG_OUT port to an interrupt line of an embedded
PowerPC™ or MicroBlaze™ processor can be used to cause a software event to occur. You
can also connect the TRIG_OUT port of one core to a trigger input port of another core in
order to expand the trigger and data capture capabilities of your on-chip debug solution.
IBA/OPB Trigger Output Logic
The IBA/OPB core implements a trigger output port called TRIG_OUT. The TRIG_OUT
port is the output of the trigger condition that is set up at run-time using the Analyzer. The
latency of the TRIG_OUT port relative to the input trigger ports is 15 clock cycles.
The TRIG_OUT port is very flexible and has many uses. For example, you can:
• Connect the TRIG_OUT port to a device pin in order to trigger external test
equipment such as oscilloscopes and logic analyzers
• Connect the TRIG_OUT port to an interrupt line of an embedded PowerPC or
MicroBlaze processor to cause a software event to occur
• Connect the TRIG_OUT port of one core to a trigger input port of another core in
order to expand the trigger and data capture capabilities of your on-chip debug
solution