20-04-2013, 03:47 PM
Computer-Aided Design Concept to Silicon
Computer-Aided Design.ppt (Size: 2.2 MB / Downloads: 50)
Mentor Graphics ASIC Design Kit (ADK)
Technology files & standard cell libraries
AMI: ami12, ami05 (1.2, 0.5 μm)
TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm)
IC flow & DFT tool support files:
Simulation
VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS)
Analog (SPICE) models (Eldo/Accusim)
Post-layout timing (Mach TA)
Digital schematic (Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018)
Synthesis to std. cells (LeonardoSpectrum)
Design for test & ATPG (DFT Advisor, Flextest/Fastscan)
Schematic capture (Design Architect-IC)
IC physical design (standard cell & custom)
Floorplan, place & route (IC Station)
Design rule check, layout vs schematic, parameter extraction (Calibre)
Xilinx/Altera FPGA/CPLD Design
Simulate designs in Modelsim
Behavioral models (VHDL,Verilog)
Synthesized netlists (VHDL, Verilog)
Requires “primitives” library for the target technology
Synthesize netlist from behavioral model
Leonardo has libraries for most FPGAs
Xilinx ISE has its own synthesis tool
Vendor tools for back-end design
Map, place, route, configure device, timing analysis, generate timing models
Xilinx Integrated Software Environment (ISE)
Altera Quartus II & Max+Plus2
Higher level tools for system design & management
Mentor Graphics FPGA Advantage
Xilinx Platform Studio : SoC design, IP management, HW/SW codesign