06-12-2012, 01:45 PM
Computer Organization
1Computer Organization.ppt (Size: 245 KB / Downloads: 117)
Computer design as an application of digital logic design procedures
Computer = processing unit + memory system
Processing unit = control + datapath
Control = finite state machine
Inputs = machine instruction, datapath conditions
Outputs = register transfer control signals, ALU operation codes
Instruction interpretation = instruction fetch, decode, execute
Datapath = functional units + registers
Functional units = ALU, multipliers, dividers, etc.
Registers = program counter, shifters, storage registers
Register Transfer
Point-to-point connection
Dedicated wires
Muxes on inputs ofeach register
Common input from multiplexer
Load enablesfor each register
Control signalsfor multiplexer
Common bus with output enables
Output enables and loadenables for each register
Register Files
Collections of registers in one package
Two-dimensional array of FFs
Address used as index to a particular word
Separate read and write addresses so can do both at same time
4 by 4 register file
16 D-FFs
Organized as four words of four bits each
Write-enable (load)
Read-enable (output enable)
Memories
Larger Collections of Storage Elements
Implemented not as FFs but as much more efficient latches
High-density memories use 1-5 switches (transitors) per bit
Static RAM – 1024 words each 4 bits wide
Once written, memory holds forever (not true for denser dynamic RAM)
Address lines to select word (10 lines for 1024 words)
Read enable
Same as output enable
Often called chip select
Permits connection of manychips into larger array
Write enable (same as load enable)
Bi-directional data lines
output when reading, input when writing
Instruction Sequencing
Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz)
Step 1: Get the ADD instruction from memory into an instruction register
Step 2: Decode instruction
Instruction in IR has the code of an ADD instruction
Register indices used to generate output enables for registers Rx and Ry
Register index used to generate load signal for register Rz
Step 3: execute instruction
Enable Rx and Ry output and direct to ALU
Setup ALU to perform ADD operation
Direct result to Rz so that it can be loaded into register