16-10-2012, 02:08 PM
Low-Power and Area-Efficient Carry Select Adder
low power and area efficient carry select adder-2012.pdf (Size: 291.98 KB / Downloads: 57)
I. INTRODUCTION
Design of area- and power-efficient high-speed data path logic systems
are one of the most substantial areas of research in VLSI system
design. In digital adders, the speed of addition is limited by the time
required to propagate a carry through the adder. The sum for each bit
position in an elementary adder is generated sequentially only after the
previous bit position has been summed and a carry propagated into the
next position.
The CSLA is used in many computational systems to alleviate the
problem of carry propagation delay by independently generating multiple
carries and then select a carry to generate the sum [1]. However,
the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA) to generate partial sum and carry by considering
carry input