28-01-2013, 02:27 PM
ISim In-Depth Tutorial
1ISim In-Depth.pdf (Size: 2.19 MB / Downloads: 55)
ISim Overview
The ISim In-Depth Tutorial provides Xilinx® designers with a detailed introduction of the
ISim simulation tool.
This tutorial is designed for running the ISim tool on a Windows environment. To run
certain steps successfully in other operation systems, some modifications might be
required.
ISim is a Hardware Description Language (HDL) simulator that lets you perform
functional (behavioral) and timing simulations for VHDL, Verilog, and mixed-language
designs. The ISim environment comprises the following key elements:
• vhpcomp (VHDL) and vlogcomp (Verilog) parsers
• fuse (HDL elaborator and linker) command
• Simulation executable
• ISim Graphical User Interface (GUI)
Tutorial Flow
This tutorial provides a flow in which you can use ISim for performing a functional
(behavioral) simulation from the Project Navigator in the ISE® Design Suite.
In this flow, you launch ISim using one of the simulation processes available in the Project
Navigator. You use the Project Navigator to create a project and implement the design in a
Xilinx FPGA.
The tutorial files contain sources that are not in Hardware Description Language (HDL),
and, thus demonstrate how Project Navigator converts these sources to HDL source files
that ISim can then compile.
Also, there is a chapter that shows you how to do the same work in a Standalone ISim
mode, where you simulate your design by creating your own ISim project files and
running the HDL linker and simulation executable in command line or batch file mode.
Design Description
The tutorial design is a demonstration of the Dynamic Reconfiguration feature of the
Virtex®-5 Digital Clock Manager (DCM).
Using the Virtex-5 DCM, the design generates an output clock using the following
relationship:
Output Clock = Input Clock * (Multiplier / Divider)
Using the Dynamic Reconfiguration Ports (DRP) in the DCM, the design lets you re-define
the Multiplier and Divider parameters to generate different output frequencies.
Design Self-Checking Test bench
To test the functionality of this design, the zip file provides a self-checking test bench.
(Refer to source file drp_demo_tb.vhd in the /sources folder.) The self-checking test
bench contains a validation routine that compares sampled values from the simulation
against expected results. The self-checking test bench provided for this design performs
the following functions.
• Generates a 100 MHz input clock for the design system clock (clk_in).
• Performs four different tests to dynamically change the output frequency of the
design. In each test, a DRP cycle is started (using the drp_start signal) to set the
output clock to a different frequency. Table 1-3, page 9 shows the expected output
frequency and Multiplier/Divider parameters used for each test.
Exploring the ISim GUI
Main Toolbar
The toolbars available in the ISim main window consist of many functionally different
options. Each toolbar offers access to frequently used commands that you can also access
from the menus. See the ISim User Guide (UG660) for more information about the GUI
components. A link to the document is available in Appendix A, Additional Resources.
The main window toolbar icons are near the top of the ISim GUI. Figure 3-2 shows the
toolbar icons in two rows. You can set the toolbars to your preference, displaying only
those toolbars you want to use.