10-04-2013, 03:25 PM
DECADE COUNTER (IC 7490)
ABSTRACT:
To study and simulate DECADE COUNTER using VHDL.
THEORY:
The decade counter counts 0 to 9.When tenth pulse reaches it reset back to 0
PROCEDURE:
The decade counter Design is entered through VHDL.
Simulate the design by applying test vectors-reset, clk and observing output d.
It is required to lock the pins and give timing constraints.
Implement the design by passing the design by various stages by mapping, time analysis and bit stream. For locking the pins write UCF file before implementation and guide the same through option set control files. Output of the implementation is .JED file, which can be directly programmed into target device FPGA.
The last step is programming in which the programme can physically download the architecture from computer to target device FPGA