27-12-2012, 05:23 PM
Low Power CMOS Design
Low Power.ppt (Size: 6.18 MB / Downloads: 219)
Low-Power Design
Design practices that reduce power consumption by at least one order of magnitude; in practice 50% reduction is often acceptable.
Low-power design methods:
Algorithms and architectures
High-level and software techniques
Gate and circuit-level methods
Test power
Components of Power
Dynamic Power
Signal transitions
Logic activity
Glitches
Short-circuit
Static Power
Leakage
Dynamic Power
Each transition of a gate consumes CV 2/2.
Methods of power saving:
Minimize load capacitances
Transistor sizing
Reduce transitions
Logic design
Glitch reduction
Designing a Glitch-Free Circuit
Maintain specified critical path delay.
Glitch suppressed at all gates by
Path delay balancing
Glitch filtering by increasing inertial delay of gates or by inserting delay buffers when necessary.
A linear program optimally combines all objectives.
Linear Program (LP)
Variables: gate and buffer delays, arrival time variables.
Objective: minimize number of delay buffers.
Subject to: overall circuit delay constraint for all input-output paths.
Subject to: minimum transient energy condition for all multi-input gates.