13-04-2013, 04:23 PM
DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER
AIM:
To design and implement the odd and even parity generator and checker using digital
logic gates.
THEORY:
PARITY CHECKER:
Parity checker will do parity checking in which the number of 0s and 1s in each word is
expected to be added. If the number of 1’s is even the check bit is 1 and if it is odd the check bit
is 0.
PARITY GENERATOR:
An even parity generator will produce a logic 1 at its output if the data word contains odd
number of 1s. If the data word contains even number of 1s then the output of the parity generator
will be low.
PROCEDURE:
1. Connections are given as per the circuit diagram on the bread board.
2. The power supply is switched ON and set a voltage of 5 Volts.
3. If the input to be given to a gate is logic ‘1’ then it is connected to +5 Volts and if the input to be given to the gate is logic ‘0’ then the particular input terminal is connected to ground.
4. Truth tables of parity generators and checkers are verified.
5. If the output is logic ‘1’ then the LED glows, if the output is logic ‘0’ then the LED does not glow.