16-08-2012, 10:07 AM
DESIGN OF CONFIGURABLE MULTI_CHANNEL SENSOR DATA PROCESSOR
DESIGN OF CONFIGURABLE MULTI_CHANNEL SENSOR DATA PROCESSOR.doc (Size: 227 KB / Downloads: 42)
ABSTRACT
The aim of this project is to model and design an efficient system that is easy to integrate with other technologies and techniques (packet based data communication, data buffering management) infrastructures at a low cost. In this project, the system would read analogue information recorded by programmable no of multi sensors in a transmitting unit attached to the system. The sensors include measure of light, temperature, Soil moisture, gas etc. The recorded data are converted to digital using analogue-to-digital converter. The processed data is compressed using proprietary RLE algorithm and sent to WI-FI or WIMAX physical layer transmitter. The transmitted data is received at the receiver and decompressed to get original data.
The increasing sensor network applications can sometimes include very sensitive information such as tracking information, personnel related information, and individual health data because of its native characteristic. The data coming from sensor is first compressed using RLE compressor algorithm. In order to send compressed sensitive sensing data reliably in to network, for this reason we implement packet based HDLC framer protocol. The basic structure is consists of Start, data, crc, end flags, represented by the sequence, are required for synchronous transmission; address field is used to identify the destination address at the receiver side. Information field contains the transported data.
The overall System Architecture will be designed using HDL language and simulation, synthesis and FPGA implementation (Translation, Mapping, Placing and Routing) will be done using various FPGA based EDA Tools.
VLSI EDATools:
Active-HDL (ALDEC): Active-HDL is an integrated environment EDA tool designed for development of VHDL, Verilog, EDIF, state, block diagram, Simulation (wave form) models and design of Synthesizable IP-Cores.
Xilinx ISE: Integrated Software Environment (ISE) enables to quickly Design, Simulation of HDL source, Synthesis of HDL based RTL design and FPGA Implementation (Placing, routing ,mapping) and Bit Stream generation.
Languages (HDL): Verilog/VHDL
Applications:
• General purpose processing like living environment, military & health.
• Extract from the features from the hyper-dimensional time series data.