22-11-2012, 06:15 PM
DESIGN OF HIGH SPEED WALLACE TREE MULTIPLIER USING ERROR TOLERANT TECHNIQUE AND ITS APPLICATION IN DIGITAL IMAGE PROCESSING
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INTRODUCTION
Multipliers are the most frequently used devices in Digital
Signal Processing (DSP) and Image processing. Fast Fourier
Transformation (FFT) is one of the important transforms
often used in image processing. The computational process
of FFT involves a large number of addition and
multiplication operations. The execution of these algorithms
requires dedicated Arithmetic and Logic Unit (ALU) and
MAC architectures. Adders and multipliers are the key
elements of these arithmetic units as they lie in the critical
path. As the computation time of a multiplier is more
compared to other datapath elements, an investigation of
various multipliers is carried out to reduce latency and
power dissipation of a processing system.
With the recent advances in technology, many researchers
have worked on the design of increasingly more efficient
multipliers. They aim at offering higher speed and lower
power consumption even while occupying reduced silicon
area. This makes them compatible for various complex and
portable VLSI circuit implementations. One such multiplier
is a regular structure array multiplier [1] proposed by
Shivaling S.
OVERVIEW OF WALLACE TREE MULTIPLICATION
A Wallace tree reduction is an efficient methodology,
easily hardware implementable that multiplies two integers,
devised by an Australian Computer Scientist Chris Wallace.
For unsigned multiplication, up to n shifted copies of the
multiplicand are added to form the result. The entire
procedure is divided into three steps: partial product (PP)
generation, partial product grouping & reduction, and final
addition.
PROPOSED WALLACE TREE MULTIPLIER
A modified multiplier architecture based on Wallace tree,
efficient in terms of power dissipation and delay without
significant increase in area has been proposed and
implemented in a 16 x16 design. Here, the partial products
are generated using AND gates. The proposed High Speed
(HS)-Wallace tree multiplier uses 4-2 and 5-2 compressor
[9] structures for the partial product addition and Error
tolerant adder [10] in the final stage of product
accumulation stage. The hierarchical decomposition of a 16
x16 Wallace tree multiplier based on proposed methodology
RESULTS AND DISCUSSION
The proposed high speed Wallace tree multiplier and
state-of the –art designs are designed using VHDL code and
synthesized using Synopsys Design Compiler. The area,
delay and total power dissipation extracted from the
simulation analysis are shown in table 2. It can be seen that
Baugh-Wooley multiplier demonstrates better performance
in terms of total power dissipation compared to all other
designs. Our proposed HS-Wallace multiplier with
ETA(m=8) demonstrates better power-delay product (PDP)
compared to standard Wallace tree, Modified Booth and
Dadda multipliers, thanks to the high speed low power
Veeramachaneni et al., compressor circuits [9] and Error
tolerant adder [10] used in partial product reduction which
contributes for a significant reduction in delay. The leakage
power dissipation of our proposed HS-Wallace tree
multiplier is 5% less compared to standard design. This is
due to the reduced gate count of the compressor circuits
employed in the architecture. In addition, our proposed HSWallace
tree with ETA (m=8) multiplier shows better area
and area-delay product (ADP) performance compared to all
other state-of-the art designs. This is due to the elimination
of carry propagation at individual stages which reduces
interconnect area and use of reduced transistor count
compressor circuits.