22-08-2013, 02:04 PM
DESIGN OF PRESCALAR FOR OPTIMIZING POWER AND VOLTAGE AND ITS APPLICATION
DESIGN OF PRESCALAR.docx (Size: 221.63 KB / Downloads: 19)
Abstract:
Power and speed are the two major constraints that we need to optimise in the world of VLSI. A frequency synthesizers consist of prescalar that operates at high frequency and consumes higher power. Here, a prescalar is designed for the low voltage and low power applications based on extended true single phase clock (E-TSPC).Using one pass transistor we can implement both the counting logic and mode selection control. As we are reducing the number of transistors, this can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops. The circuit simplicity leads to a shorter critical path and reduced power consumption. Also the proposed design is capable of working at a maximum frequency when the supply voltage is low. As an application of this prescalar phase locked loop can be designed to produce the different frequencies at the output to our requirement by eliminating the phase error.
INTRODUCTION
The fundamental module of frequency synthesizers is high speed divide-by-N/N+1 counter which is also called as prescalar. The design of this prescalar plays a major role in the frequency synthesizer because it operates at a higher frequency and consumes higher power consumption. True Single Phase Clock high speed FF based, divide-by-N/N+1 counter design using current mode logic(CML) latches are well known for the low power consumption but their application is limited to low frequencies. This prescalar synchronous[1] circuit is formed by the D Flip flops and the additional logic gates. Current mode logic (CML) which is used in the conventional method suffer from disadvantage of the large load capacitance. Due to this not only the maximum operating frequency and current driven capabilities are decreased but also increases the power consumption.
TRADITIONAL E-TSPC BASED DESIGN OF 2/3 PRESCALAR
The Extended-true single phase clock operates at the high frequency when compared to the traditional TSPC. Since the circuitry can be easily built by two D-FFs and the additional logic gates, the delay and the power consumption can be reduced. The control signal DC is used as the mode selection control.
MODIFIED E-TSPC BASED DESIGN OF 2/3 PRESCLAR
In this design the two flip flops (FFs) and the AND gate are common as the previous design. But the OR gate for the divide control is replaced with the single pass transistor (either pMOS or nMOS) which acts as a switch. And there is a negation bubble at the AND gate’s input. Thus the one input of the AND gate is inverted.
CONCLUSION
The power and voltage are successfully optimised using the E-TSPC. The Modified design will simplifies the control logic with one pMOS transistor. This circuit simplicity leads to a shorter critical path and reduced power consumption. We focus on low VDD operations without sacrificing the speed performance Hence maximum frequency can be achieved by reducing the power consumption. So, a prescalar with the power reduction is used in the phase locked loop, which in turn gives the various frequencies at the output with phase match.