28-11-2012, 02:47 PM
DS12C887 Real Time Clock
Real Time Clock.pdf (Size: 195.19 KB / Downloads: 20)
FEATURES
Drop-in replacement for IBM AT computer
clock/calendar
Pin compatible with the MC146818B and
DS1287
Totally nonvolatile with over 10 years of
operation in the absence of power
Self-contained subsystem includes lithium,
quartz, and support circuitry.
Counts seconds, minutes, hours, days, day of
the week, date, month, and year with leap
year compensation valid up to 2100
Binary or BCD representation of time,
calendar, and alarm
12– or 24–hour clock with AM and PM in
12–hour mode
Daylight Savings Time option
Selectable between Motorola and Intel bus
timing
Multiplex bus for pin efficiency
Interfaced with software as 128 RAM
locations
– 15 bytes of clock and control registers
– 113 bytes of general purpose RAM
DESCRIPTION
The DS12C887 Real Time Clock plus RAM is designed as a direct upgrade replacement for the DS12887
in existing IBM compatible personal computers to add hardware year 2000 compliance. A century byte
was added to memory location 50, 32h, as called out by the PC AT specification. A lithium energy
source, quartz crystal, and write-protection circuitry are contained within a 24–pin dual in-line package.
As such, the DS12C887 is a complete subsystem replacing 16 components in a typical application. The
functions include a nonvolatile time-of-day clock, an alarm, a one-hundred-year calendar, programmable
interrupt, square wave generator, and 113 bytes of nonvolatile static RAM. The real time clock is
distinctive in that time-of-day and memory are maintained even in the absence of power.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS12C887. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts are
applied within normal limits, the device is fully accessible and data can be written and read. When VCC is
below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues
unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are
switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of ±1
minute per month at 25°C regardless of the voltage input on the VCC pin.
POWER-DOWN/POWER-UP CONSIDERATIONS
The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the
DS12C887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms,
provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A).
This time period allows the system to stabilize after power is applied. When VCC falls below 4.25 volts,
the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin.
The DS12C887 is, therefore, write-protected. When the DS12C887 is in a write-protected state, all inputs
are ignored and all outputs are in a high impedance state. When VCC falls below a level of approximately
3 volts, the external VCC supply is switched off and an internal lithium energy source supplies power to
the Real Time Clock and the RAM memory.
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by reading the appropriate memory bytes. The time,
calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten
time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before
writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a
logic one to prevent updates from occurring while access is being attempted. In addition to writing the ten
time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of
Register B must be set to the appropriate logic level. All ten time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be cleared after the data mode bit has been written to
allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock
makes all updates in the selected mode. The data mode cannot be changed without reinitializing the ten
data bytes. Table 2 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The
24–12 bit cannot be changed without reinitializing the hour locations. When the 12–hour format is
selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar,
and alarm bytes are always accessible because they are double buffered. Once per second the eleven bytes
are advanced by one second and checked for an alarm condition. If a read of the time and calendar data
occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The
probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible
incorrect time and calendar reads are covered later in this text.