19-12-2012, 05:45 PM
8051 TUTORIAL
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INTRODUCTION
Figure 1.1 shows a functional block of the internal operation of an 8051
microcomputer. The internal components of the chip are shown within the broken line
box.
A quick comparison with the well known Pentium processor
A modern PC is powered by a Pentium processor (or equivalent), which is really a
very powerful microprocessor. Where the 8051 microcontroller represents the low
end of the market in terms of processing power, the Pentium processor is one of the
most complex processors in the world. Figure 1.3 shows a simplified block diagram
of the Pentium processor and a simple comparison between the 8051 and the Pentium
is given in the table below.
MEMORY AND REGISTER ORGANISATION
The 8051 has a separate memory space for code (programs) and data. We will refer
here to on-chip memory and external memory as shown in figure 1.5. In an actual
implementation the external memory may, in fact, be contained within the
microcomputer chip. However, we will use the definitions of internal and external
memory to be consistent with 8051 instructions which operate on memory. Note, the
separation of the code and data memory in the 8051 architecture is a little unusual.
The separated memory architecture is referred to as Harvard architecture whereas
Von Neumann architecture defines a system where code and data can share common
memory.
Bit Addressable RAM: 20h to 2Fh
The 8051 supports a special feature which allows access to bit variables. This is
where individual memory bits in Internal RAM can be set or cleared. In all there are
128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0
or 1. A bit variable can be set with a command such as SETB and cleared with a
command such as CLR.
Stack Pointer
The Stack Pointer, SP, is an 8-bit SFR register at address 81h. The small address field
(8 bits) and the limited space available in the Internal RAM confines the stack size
and this is sometimes a limitation for 8051 programmes. The SP contains the address
of the data byte currently on the top of the stack. The SP pointer in initialised to a
defined address. A new data item is ‘pushed’ on to the stack using a PUSH instruction
which will cause the data item to be written to address SP + 1. Typical instructions,
which cause modification to the stack are: PUSH, POP, LCALL, RET, RETI etc.. The
SP SFR, on start-up, is initialised to 07h so this means the stack will start at 08h and
expand upwards in Internal RAM. If register banks 1 to 3 are to be used the SP SFR
should be initialised to start higher up in Internal RAM.