11-12-2012, 06:47 PM
Delay Modeling in VHDL
Delay Modeling.pdf (Size: 1,002.06 KB / Downloads: 30)
Types of Delay in VHDL
•All VHDL signal assignmentstatements prescribe an amount of timethat must transpire before the signal assumes its new value
•This prescribed delay can be in one of three forms:
•Transport --prescribes propagation delay only
•Inertial--prescribes minimum input pulse width and propagation delay
•Delta--the defaultif no delay time is explicitly specified
Concepts of Delays and Timing
•The time dimension in the signal assignment refers to simulation time in a discrete event simulation
•There is a simulation time clock
•When a signal assignment is executed, the delay specified is added to current simulation timeto determine when new value is applied to signal
–Schedules a transaction for the signal at that time
Variables
•Can be altered using variable assignment statements
•Updating takes place immediately
•Can be declared only within Processes and Functions
•Variables Inside Processes
•Variables inside processes are static
•Assigned value is stored till next call.
•Variables inside functions and procedures are not static