25-08-2017, 09:32 PM
Design Technologies for Low Power VLSI
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Abstract
Low power has emerged as a principal theme in today’s electronics industry.
The need for low power has caused a major paradigm shift where power dissipation
has become as important a consideration as performance and area. This
article reviews various strategies and methodologies for designing low power circuits
and systems. It describes the many issues facing designers at architectural,
logic, circuit and device levels and presents some of the techniques that have been
proposed to overcome these difficulties. The article concludes with the future
challenges that must be met to design low power, high performance systems.
Motivation
In the past, the major concerns of the VLSI designer were area, performance,
cost and reliability; power consideration was mostly of only secondary
importance. In recent years, however, this has begun to change and, increasingly,
power is being given comparable weight to area and speed considerations. Several
factors have contributed to this trend. Perhaps the primary driving factor has
been the remarkable success and growth of the class of personal computing
devices (portable desktops, audio- and video-based multimedia products) and
wireless communications systems (personal digital assistants and personal communicators)
which demand high-speed computation and complex functionality
with low power consumption.
Sources of Power Dissipation
Power dissipation in CMOS circuits is caused by three sources: 1) the leakage
current which is primarily determined by the fabrication technology, consists
of reverse bias current in the parasitic diodes formed between source and drain diffusions and the bulk region in a MOS transistor as well as the subthreshold
current that arises from the inversion charge that exists at the gate voltages below
the threshold voltage, 2) the short-circuit (rush-through) current which is due to
the DC path between the supply rails during output transitions and 3) the charging
and discharging of capacitive loads during logic changes.
Low Power Design Space
The previous section revealed the three degrees of freedom inherent in the
low-power design space: voltage, physical capacitance, and data activity. Optimizing
for power entails an attempt to reduce one or more of these factors. This
section briefly discusses each of these factors, describing their relative importance,
as well as the interactions that complicate the power optimization process.
Voltage
Because of its quadratic relationship to power, voltage reduction offers the
most effective means of minimizing power consumption. Without requiring any
special circuits or technologies, a factor of two reduction in supply voltage yields
a factor of four decrease in power consumption. Furthermore, this power reduction
is a global effect, experienced not only in one sub-circuit or block of the
chip, but throughout the entire design. Because of these factors, designers are
often willing to sacrifice increased physical capacitance or circuit activity for
reduced voltage. Unfortunately, we pay a speed penalty for supply voltage reduction,
with delays drastically increasing as Vdd approaches the threshold voltage Vt
of the devices. This tends to limit the useful range of Vdd to a minimum of about
2-3 Vt.
Physical Capacitance
Dynamic power consumption depends linearly on the physical capacitance
being switched. So, in addition to operating at low voltages, minimizing capacitances
offers another technique for minimizing power consumption. In order to
consider this possibility we must first understand what factors contribute to the
physical capacitance of a circuit.
Power dissipation is dependent on the physical capacitances seen by individual
gates in the circuit. Estimating this capacitance at the behavioral or logical
levels of abstraction is difficult and imprecise as it requires estimation of the load
capacitances from structures which are not yet mapped to gates in a cell library;
this calculation can however be done easily after technology mapping by using
the logic and delay information from the library.
Interconnect plays an increasing role in determining the total chip area,
delay and power dissipation, and hence, must be accounted for as early as possible
during the design process. The interconnect capacitance estimation is however
a difficult task even after technology mapping due to lack of detailed place
and route information. Approximate estimates can be obtained by using information
derived from a companion placement solution [49] or by using stochastic /
procedural interconnect models [50]. Interconnect capacitance estimation after
layout is straight-forward and in general accurate.
Switching Activity
In addition to voltage and physical capacitance, switching activity also
influences dynamic power consumption. A chip may contain an enormous amount
of physical capacitance, but if there is no switching in the circuit, then no
dynamic power will be consumed. The data activity determines how often this
switching occurs. There are two components to switching activity: fclk which
determines the average periodicity of data arrivals and E(sw) which determines
how many transitions each arrival will generate. For circuits that do not experience
glitching, E(sw) can be interpreted as the probability that a power consuming
transition will occur during a single data period. Even for these circuits,
calculation of E(sw) is difficult as it depends not only on the switching activities
of the circuit inputs and the logic function computed by the circuit, but also on the
spatial and temporal correlations among the circuit inputs. The data activity
inside a 16-bit multiplier may change by as much as one order of magnitude as a
function of input correlations [41].
Calculation of Switching Activity
Calculation of the switching activity in a logic circuit is difficult as it
depends on a number of circuit parameters and technology-dependent factors
which are not readily available or precisely characterized. Some of these factors
are described next.