25-01-2013, 12:47 PM
Design and Implementation of an FPGA-based Real-Time Face Recognition System
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Abstract
Face recognition systems play a vital role in many
applications including surveillance, biometrics and security. In
this work, we present a complete real-time face recognition
system consisting of a face detection, a recognition and a
downsampling module using an FPGA. Our system provides an
end-to-end solution for face recognition; it receives video input
from a camera, detects the locations of the face(s) using the
Viola-Jones algorithm, subsequently recognizes each face using
the Eigenface algorithm, and outputs the results to a display.
Experimental results show that our complete face recognition
system operates at 45 frames per second on a Virtex-5 FPGA.
INTRODUCTION
Face recognition is a challenging research area in terms
of both software (developing algorithmic solutions) and
hardware (creating physical implementations). A number of
face recognition algorithms have been developed in the past
decades [1] with various hardware implementations [2], [3],
[4], [5], [6], [7]. All previous hardware implementations
assume that the input to the face recognition system is an
unknown face image. Current hardware based face recognition
systems are limited since they fail if the input is not
a face image. A practical face recognition system should
not require the input to be a face, instead would recognize
face(s) from any arbitrary video which may or may not
contain face(s) potentially in the presence of other objects.
Therefore, an ideal face recognition system should first have
a face detection subsystem which is necessary for finding
a face in an arbitrary frame, and also a face recognition
subsystem which identifies the unknown face image.
Experimental Results
We present experimental results from set1 and set2. Figure
3 shows the performance comparisons between the software
and hardware implementations of the face recognition
subsystem using 10, 20, 25, 50 and 100 images from set1.
When using 100 images, the face recognition subsystem
achieves an average speed up of 15X over the equivalent
software implementation. The software experiment was done
on multi-core machine machine with Core2 Duo CPU running
at 3.33 GHz with 4 GB RAM.
Figure 4 (a) and (b) shows the latency and the latency
cycles respectively for 40, 50 and 60 face images from set2
with pipelined and non-pipelined implementations. The device
utilization summary when using set2 with pipelined and
non-pipelined implementations is also shown in Figure 4 ©
in number of slices, LUTs, RAMs (BRAMs), and DSP48s.
CONCLUSION
This paper presented the design and implementation of
a complete FPGA-based real-time face recognition system
which runs at 45 frames per second. This system consists
of three subsystems: face detection, downsampling and face
recognition. All of the modules are designed and implemented
on a Virtex-5 FPGA. We presented the architectural
integration of the face detection and face recognition subsystems
as a complete system on physical hardware. Different
experimental results of the face recognition subsystem are
presented for pipelined and non-pipelined implementations.