14-06-2012, 11:10 AM
Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter
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Abstract
This paper presents a functional design and modeling
of a successive approximation analog to digital converter(
SAR ADC). The SAR ADC is described in VHDL-AMS
behavior models and transistor level circuit netlists using the
0.13m technology and supply voltage equals to 1.2V.
INTRODUCTION
The trends in many energy-limited applications such as
MEMS sensors ,micro-robotics and wireless sensor network
add more challenges to reduce the power consumption. Power
saving can be achieved in ADC by choosing the best
architecture level among different ones presented. One of the
most known ADC architecture for low power application is
the Successive Approximation ADC.
SAR ADC ARCHITECTURE
In Fig. 1, we can see how the different parts of the SAR
ADC are connected. In our topology, the signal is sampled
in the first clock cycle and is converted in the next N clock
cycle, where N is the number of bits. We use the DAC in the
first clock cycle for Sampling the signal so that we decrease
the active blocks in our architecture to reduce the power
consumed. Our DAC contains two chains of binary weighted
capacitors so that we sample the signal in a differential way
. The differential outputs of the DAC are connected to the
comparator input terminals as in Fig.
CONCLUSION AND SIMULATION RESULT
From the simulation results of differential 8-bit SAR ADC
with three references and sampling frequency equals to
111KHz, we can see in Fig 6 the three modes of operation and
the comparator output that changes the control unit outputs
thus the corresponding voltages on the DAC top plates. In
Fig. 7, We see how the SAR ADC converts the 1.4KHz
sinusoidal wave. We are interested in this architecture because
of its good resolution and low power consumption.