10-09-2013, 12:40 PM
Design and Verification of Area Efficient High-Speed Carry Select Adder
Design and Verification.pdf (Size: 655.39 KB / Downloads: 72)
Abstract
Design of area efficient and high-speed data
path logic systems forms the largest areas of research
in VLSI system design. In digital adders, the speed of
addition is limited by the time required to transmit a
carry through the adder. Carry Select Adder (CSLA)
is one of the fastest adders used in many data-
processing processors to perform fast arithmetic
functions. From the structure of the CSLA, it is clear
that there is span for reducing the area in the CSLA.
This work uses a simple and efficient gate-level
modification to drastically reduce the area and power
of the CSLA. Based on this modification 8, 16, 32, 64
and 128-bit square-root CSLA (SQRT CSLA)
architectures have been developed and compared with
the regular SQRT CSLA architecture. The proposed
design has reduced area as compared with the regular
SQRT CSLA. This work estimates the performance of
the proposed designs in terms of delay, area are
implemented in Xilinx ISE.
INTRODUCTION
Area and power reduction in data path logic
systems are the main area of research in VLSI system
design. High-speed addition and multiplication has
always been a fundamental requirement of high-
performance processors and systems. In digital adders, the
speed of addition is limited by the time required to
propagate a carry through the adder. The sum for each bit
position in an elementary adder is generated sequentially
only after the previous bit position has been summed and
a carry propagated into the next position. The major speed
limitation in any adder is in the production of carries and
many authors have considered the addition problem.
BASIC FUNCTION AND STRUCTURE OF BEC
LOGIC
The delay and area evaluation methodology
considers all gates to be made up of AND, OR, and
Inverter, each having delay equal to 1 unit and area equal
to 1 unit. We then add up the number of gates in the
longest path of a logic block that contributes to the
maximum delay. The area evaluation is done by counting
the total number of AOI gates required for each logic
block. Based on this approach, the CSLA adder blocks of
2:1 mux, Half Adder (HA), and FA are evaluated and
listed in Table I.
The basic work is to use Binary to Excess-1
Converter (BEC) instead of RCA with Cin=1 in the
regular CSLA to achieve lower area and power
consumption. The main advantage of this BEC logic
comes from the lesser number of logic gates than the n-bit
Full Adder (FA) structure As stated above the main idea
of this work is to use BEC instead of the RCA with Cin=1
in order to reduce the area and power consumption of the
regular CSLA. To replace the n-bit RCA, an n+1-bit BEC
is required. A structure and the function table of a 4-bit
BEC are shown in Figure.2 and Table .2, respectively.
IMPLEMENTATION RESULTS
The design proposed in this paper has been
developed using Verilog-HDL and synthesized in Xilinx
ISE 9.2i. For each word size of the adder, the same value
changed dump (VCD) file is generated for all possible
input conditions and imported the same to Xilinx ISE 9.2i
Power Analysis to perform the power simulations. The
similar design flow is followed for both the regular and
modified SQRT CSLA. Table 5 exhibits the simulation
results of both the CSLA structures in terms of delay and
area.
CONCLUSION
A simple approach is proposed in this paper to
reduce the area of SQRT CSLA architecture. The reduced
number of gates of this work offers the great advantage in
the reduction of area. The compared results show that the
modified SQRT CSLA has a delay (only3.76%), but the
area of the 128-bit modified SQRT CSLA are
significantly. The area-delay product of the proposed
design show a decrease for 16 and 128-bit sizes which
indicates the success of the method and not a mere
tradeoff of delay for power and area. The modified CSLA
architecture is therefore, low area, simple and efficient for
VLSI hardware implementation.
As the functional verification decides the quality
of the silicon, we spend 60% of the design cycle time only
for the verification/simulation. This project helps one to
understand the complete functional verification process of
complex ASICs an SoC’s and it gives opportunity to try
the latest verification methodologies, programming
concepts like Object Oriented Programming of Hardware
Verification Languages and sophisticated EDA tools, for
the high quality verification.