19-01-2013, 04:10 PM
Design and implementation of pattern generator for circuit under test using VERILOG
Design and implementation.doc (Size: 27 KB / Downloads: 31)
ABSTRACT
Test Pattern generation has long been carried out by using Linear Feedback Shift Registers (LFSR’s). LFSR’s are a series of flip-flop’s connected in series with feedback taps defined by the generator polynomial. The seed value is loaded into the outputs of the flip-flops. The only input required to generate a random sequence is an external clock where each clock pulse can produce a unique pattern at the output of the flip-flops.
This random sequence at the output of the flip-flops can be used as a test pattern. The number of inputs required by the circuit under test must match with the number of flip-flop outputs of the LFSR. This test pattern is run on the circuit under test for desired fault coverage.