04-04-2012, 02:52 PM
TRAFFIC LIGHT CONTROLLER
TRAFFIC LIGHT CONTROLLER.doc (Size: 39 KB / Downloads: 74)
AIM:
To design and simulate a traffic light controller using verilog HDL.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software.
• PC with Windows XP
ALGORITHM:
• Create a verilog file.
• Assign port names.
• Write verilog program.
• Check syntax.
• Create test bench waveform and give input.
• Simulate the traffic light controller using ISE simulator.
THEORY:
Consider a controller for traffic at the intersection of four roads. Consider P1, P2, P3, P4 as four roads and Pl as pedestrian. The road has following states.
• GREEN-10011
• YELLOW-01000
• RED-00100
The pedestrian
• GREEN-0000
• Red-1111
First the road p1 is green and all other roads p2, p3, p4 and PL are red. After a some delay p1 is turn to yellow and then red the traffic signal on p2 is green. After a delay p2 is turn to yellow and then red the signal on p3 is green. Then p3 is changed to yellow and then red the signal on p4 is changed to green. After a delay p4 is turn to yellow and then red the pedestrian light PL is green after a delay PL is turn to green then routine will continue.
To simulate this module launch into modelsim. In wave window force clk as clock and reset is low for 1ns after change to high and run. See the result in wave window.
PROGRAM:
Code:
module traffic(clk, reset, p1, p2, p3, p4, pt);
input clk;
input reset;
output [4:0] p1; // d5,d4,d3,d2,d1
output [4:0] p2; // d10,d9,d8,d7,d6
output [4:0] p3; // d15,d14,d13,d12,d11
output [4:0] p4; // d20,d19,d18,d17,d16
output [3:0] pt; // dl1,dl2,dl3,dl4,dl5,dl6,dl7,dl8 (Pedestrain)
reg [4:0] p1;
reg [4:0] p2;
reg [4:0] p3;
reg [4:0] p4;
reg [3:0] pt;
reg [31:0] sig;
always @ (posedge clk or negedge reset)
begin
if (reset == 1'b0) begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
sig <= 8'h00000000;
end
else begin
sig <= sig + 1;
case (sig[29:24])
6'b000000 : begin
p1 <= 5'b10011; // d5,d4,d3,d2,d1 (Green)
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b000100 : begin
p1 <= 5'b01000; //Yellow
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b001000 : begin
p1 <= 5'b00100; // d10,d9,d8,d7,d6
p2 <= 5'b10011; //Green
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b001100 : begin
p1 <= 5'b00100;
p2 <= 5'b01000; //Yellow
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b010000 : begin
p1 <= 5'b00100; // d15,d14,d13,d12,d11
p2 <= 5'b00100;
p3 <= 5'b10011; //Green
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b010100 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b01000; //yellow
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b011000 : begin
p1 <= 5'b00100; // d20,d19,d18,d17,d16
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b10011; //Green
pt <= 4'b1111;
end
6'b011100 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b01000; //Yellow
pt <= 4'b1111;
end
6'b100000 : begin
p1 <= 5'b00100; // dl1,dl2,dl3,dl4,dl5,dl6,dl7,dl8
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b0000; //Pedestrain
end
6'b100100 : sig <= 8'h00000000;
default : begin
end
endcase
end
end
endmodule
Thus traffic light controller using verilog HDL is designed and simulated using ISE simulator