14-09-2013, 03:15 PM
Design of 8-to-3 encoder (without and with parity) usingVerilog HDL
Aim:
1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and
structural modeling style in Verilog using a Test bench.
2. Synthesize each one of them on two different EDA tools.
Apparatus required:
Electronics Design Automation Tools used:
ii)Xilinx Spartan 3E FPGA +CPLD Board
Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST
iii) Synthesis tool or LeonardoSpectrum Synthesis Tool
iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
fromSimulation to Implementation to download onto FPGA).
v) JTAG cable
vi) Adator 5v/4A
THEORY:
An encoder is a digital circuit which performs the inverse of decoder.An encoder has 2^N input
lines and N output lines.In encoder the output lines genrate the binary code corresponding to
input value.The decimal to bcd encoder usually has 10 input lines and 4 ouput lines.The
decoder decimal data as an input for decoder an encoded bcd ouput is available at 4 output
lines.Priority encoder is a special type of encoder in which multiple bits at the input can be asserted.
The response at the output is however defined by the priority rule, defined previously. Priority
encoders have vast application in different client-server systems. In client-server systems
decision is made to grant a service based on the priority of any specific client.
Here is a verilog code for an 8:3 priority encoder. It grants the highest priority to the "most left
sided bit in the input word". For example in data word "00010101" the highest priority is carried
by the most left sided one, appearing at the fourth (counting from left side). So all the other bits
that come next to it will be discarded or in other words will not be taken into account. Verilog
implementation has been done using "casex" statement.