29-08-2013, 04:34 PM
Design of Area and Power Efficient Modified Carry Select Adder
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ABSTRACT
Adders are one of the widely used digital components in digital
integrated circuit design. The Carry Select Adder (CSA)
provides a good compromise between cost and performance in
carry propagation adder design. However, conventional CSA is
still area-consuming due to the dual ripple carry adder (RCA)
structure. In this paper, modification is done at gate-level to
reduce area and power consumption. The Modified Carry
Select-Adder (MCSA) is designed for 8-bit, 16-bit, 32-bit and
64-bit and then compared with conventional CSA respective
architectures. MCSA shows reduction in area and power
consumption in comparison with conventional CSA with small
increase in delay.
INTRODUCTION
Addition is the heart of computer arithmetic, and the arithmetic
unit is often the work horse of a computational circuit. They are
the necessary component of a data path, e.g. in microprocessors
or a signal processor. There are many ways to design an adder.
The Ripple Carry Adder (RCA) provides the most compact
design but takes longer computing time. If there is N-bit RCA,
the delay is linearly proportional to N. Thus for large values of
N the RCA gives highest delay of all adders. The Carry Look-
Ahead Adder (CLA) gives fast results but consumes large area.
If there is N-bit adder, CLA is fast for N
≤4, but for large values
of N its delay increases more than other adders. So for higher
number of bits, CLA gives higher delay than other adders due to
presence of large number of fan-in and a large number of logic
gates. The Carry Select Adder (CSA) provides a compromise
between small area but longer delay RCA and a large area with
shorter delay CLA.
CARRY SELECT ADDER
Carry Select Adders (CSA) is one of the fastest adders used in
many data-processing processors to perform fast arithmetic
functions. The carry-select adder partitions the adder into
several groups, each of which performs two additions in parallel.
Therefore, two copies of ripple-carry adder act as carry
evaluation block per select stage. One copy evaluates the carry
chain assuming the block carry-in is zero, while the other
assumes it to be one. Once the carry signals are finally
computed, the correct sum and carry-out signals will be simply
selected by a set of multiplexers. The 4-bit adder block is RCA.
The Figure 1 shows 16-bit conventional Carry Select adder.
SIMULATION RESULTS AND
COMPARISON
The various adders are designed using Verilog language in
Xilinx ISE Navigator 12.4 .And all the simulations are
performed using Xilinx ISim simulator. The performance of
proposed MCSA is analysed and compared against the
conventional CSA designs. The number of gates used in the
design indicates the area of design. The power consumption is
measured in terms of total power and dynamic power . The
speed of the adder is estimated by the delay involved in the
design. It can be seen from Table 4 that area and power
consumption of MCSA is less than that of conventional CSA,
whereas delay is more in MCSA. This shows that area and
power consumption of MCSA is reducing at the cost of small
decrease in speed. As the number of gates used in the design of
MCSA are fewer than the conventional CSA. The reduced
number of gates of the MCSA offers a great advantage in the
reduction of area and total power consumption
CONCLUSION
In this paper, a Modified Carry Select-Adder (MCSA) is
designed by using single Ripple Carry Adders (RCA) and
Binary to Excess-1 Converter (BEC) instead of using dual RCAs
to reduce area and power consumption with small speed penalty.
The reduced number of gates of this work offers the great
advantage in the reduction of area and also the total power. The
MCSA architecture for 8-bit, 16-bit, 32-bit and 64-bit is
designed and then compared with conventional CSA respective
architectures. MCSA shows reduction in area and power
consumption in comparison with conventional CSA with small
increase in delay. The synthesis results shows that the reduction
in area and power consumption increases with increasing word
size of adder whereas delay decreases with increasing word size.
It is also analyzed that MCSA for 8-bit, 16-bit, 32-bit and 64-bit
shows an increasing order of reduction in area by 16.5 %,
20.62%, 22.21%, 22.92% and power consumption by 8%, 14%,
16%, 17 % respectively. Whereas, the delay overhead for 8-bit,
16-bit, 32- bit and 64-bit MCSA indicates decreasing trend with
bit size as 15%, 9%, 6.9% and 4% respectively. Therefore,
MCSA architecture is low area, low power, simple and efficient
for VLSI hardware implementation.