09-11-2012, 04:01 PM
Design of Self-timed Asynchronous Booth’s multiplier
Design of Self-timed Asynchronous Booth’s multiplier.pdf (Size: 72.26 KB / Downloads: 28)
Introduction
Asynchronous design methodology has been studied
actively in recent years. The main characteristic is using local
distributed handshake signals instead of a global clock to
control the operation of each function block in the system.
Asynchronous methodology has certain advantages over its
counterpart, the synchronous design [2]. It does not have the
problem of clock skew since it does not have global clock.
Other potential advantages include low power consumption
and average-case delay performance.
In self-timed asynchronous circuits, each functional
block is controlled by some handshake circuit such that each
functional block is operated in correct order. Each functional
block should also be able to acknowledge the completion of
its operation to the handshake control circuit. The
acknowledgement of the completion can be inherent in data
signals or separated as a “complete” signal. In our multiplier
design, SCCVSL (single-rail CMOS cascode voltage switch
logic) [3] is used to generate the necessary “complete” signal.
Implementation
Modified Booth’s Algorithm [1]
In the modified booth’s algorithm, an encoding
technique is used to reduce the number of partial products.
Different encoding techniques result different reductions of
number of partial product. In our 8 × 8 multiplier, the
multiplier (B) is divided into 4 substrings of 3 bits, with
adjacent groups sharing a common bit. A ‘0’ is also padded
to the right of the multiplier B such that 4 complete
substrings can be formed. Each substring is then decoded to
give Y from the multiplicand (A) according the Table 1. With
the above encoding scheme, 4 partial product will be
generated for 8-bit × 8-bit signed multiplication. Each partial
product is equal to Y multiplied by a scaling factor F. The
scaling factor is equal to 1, 4, 16, 64 for the first, second,
third and forth operation respectively. The final product is
equal to the sum of the four partial products.
the block diagram of the self-timed
asynchronous booth’s multiplier. The multiplier requires 4
cycles of operation to generate the final product. Each cycle
generates one partial product and accumulates it with the
partial product generated in pervious cycles. The multiplier is
divided into two stages. The first stage mainly contains
load/shift registers and booth’s decoder. This stage is used to
generate the partial product. The second stage mainly
contains a 16-bit ripple-carry adder. This is used to add up all
the partial products generated in each operation cycle.
Besides the two stages, a central handshake controller is also
included. It not only generate the internal request and reset
signal for the two stages, but also handles the external request
and complete signal.
Conclusion
A self-timed asynchronous multiplier had been
implemented. It performs average case delay. And also, by
using modified booth’s algorithm, the number of partial
products is reduced. As a result, the speed of the multiplier is
improved.