10-05-2014, 03:00 PM
Design of a CDMA System in FPGA Technology
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Abstract
This paper presents the design and implementation of
a chaos-based code division multiple access (CDMA) system in
FPGA (field programmable gate array) technology. A chaos-
based CDMA system uses chaotic sequences as spreading codes
to encode each user’s message. The user’s message can again be
separated by the orthogonal property of chaotic sequences at the
receiver. Chaos-based communication systems offer higher
security than conventional CDMA systems. The system is
implemented in Altera Cyclone EP1C20 Nios II Development
Board. This paper also presents a system performance analysis
by obtaining BER (bit error rate) results from the prototype,
computer software simulation and theoretical calculation. The
effects of changing the number of users, spreading factor and the
inclusion of FIR (finite impulse response) filters on the system
performance have been investigated. Real-time transmission of
music signals is demonstrated using the prototype implemented
in Altera APEX20KE DSP Development Board.
INTRODUCTION
Over the past five to ten years, communication systems
have been developing rapidly especially in the wireless and
cellular network arena [1]. As user demand grows,
conventional communication systems such as time-division-
multiple-access (TDMA), frequency-division-multiple-access
(FDMA) and space-division-multiple-access (SDMA) are
becoming inadequate for some application in today’s
communication requirements. Consequently, a new system
called code-division-multiple-access (CDMA) is proposed to
replace the aforementioned systems. This new system utilises
the spread spectrum technique where the message signals can
occupy both the time and frequency domains simultaneously,
thus the system capacity is significantly increased. CDMA
system also offers mitigation to multi-path fading, reduction in
frequency planning and signal quality sharing between users
[1], [2]. FPGA (field programmable gate arrays) nowadays
offer fast code evaluation speed over a PC-based environment.
This allows the generation of BER results in a fast and efficient
way.
BACKGROUND THEORY OF CDMA
In a direct sequence scheme, the original message symbol
(+1 or -1) is multiplied by sequence of codes. These are
referred to as the spreading codes. Depending on the type of
modulation method, different types of spreading codes are
used. Next, all user encoded messages sn(t) are summed up as
s(t) and transmitted through the channel. In our project, we
have included two finite impulse response (FIR) filters at the
transmitter and receiver respectively (Fig. 1). The purpose of
those will be discussed later in Section III. Once the corrupted
composite signal x(t) has reached the receiver, the receiver
decodes the signal into binary sequences.
FIR FILTER DESIGN
A finite impulse response can be thought of as an infinite
impulse response being windowed, leaving the centre region
with the two tails cut off as shown in Fig. 3. The aim of
incorporating this filter into our system design is to firstly
reduce the transmission bandwidth at the transmitter so it uses
less channel resources. Secondly, it is desirable to reduce the
level of noise presented at the receiver.
At the transmitter, this filter shapes the rectangular pulses
into smoothed waveforms (Fig. 4). By smoothing the sharp
edges of the rectangular pulses, the bandwidth is significantly
reduced. At the receiver, we sample the received chips at time
instances which correspond to the original rectangular pulses to
recover the original chip code.
HARDWARE IMPLEMENTATION
The target FPGA device is the Altera Cyclone EP1C20
Nios II Development Board. The Altera Cyclone device is
chosen for this project because system performance analysis
tools can be developed with ease by using the Nios II processor.
Furthermore, system-on-a-programmable-chip (SOPC) builder
and Ethernet interface are available with Nios II Development
boards [5]. The hardware is designed in Altera Quartus II using
Verilog HDL, VHDL and schematic design entry. The
complexity of the prototype depends on the hardware resources
that are available on the FPGA device. Some hardware devices,
such as the Stratix family, have DSP (digital signal processing)
blocks that can be implemented into efficient multipliers and
adders, and thus avoid the implementation of these functional
blocks using logic elements [8]. Cyclone does not have DSP
blocks, but it has M4K blocks that can be used to implement
soft multipliers.
CONCLUSIONS
It is concluded that a transceiver structure of the CDMA
system using CPSK modulation scheme was implemented in
FPGA using the Cyclone EP1C20F400C7 development board.
It was shown that the use of DSP blocks can significantly
reduce the number of logic elements which can be used to
further expand system functionalities. Therefore, it is suggested
that a hybrid hardware prototype including DSP blocks and
FPGA would be an ideal hardware platform for implementing
the system. Also, it is desirable to incorporate soft-core design
into the hardware design to allow for logic elements reduction.
The addition of FIR filters provides a better system
performance, however, because as inter-user interference
increases, the system performs decreases. Therefore,
mechanisms which minimise inter-user interference should be
investigated. The performance of FIR filters should be
evaluated through proper up/down conversion devices. As the
spreading factor increases, the system performs better with
compensated transmission rate and bandwidth requirement.
Real time signal transmission was successfully implemented
using the prototype. Finally, synchronisation between the
transmitter and the receiver is to be investigated.