30-09-2013, 04:40 PM
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
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Abstract
Given the critical role of motion estimation (ME) in
a video coder, testing such a module is of priority concern. While
focusing on the testing of ME in a video coding system, this work
presents an error detection and data recovery (EDDR) design,
based on the residue-and-quotient (RQ) code, to embed into ME
for video coding testing applications. An error in processing
elements (PEs), i.e. key components of a ME, can be detected
and recovered effectively by using the proposed EDDR design.
Experimental results indicate that the proposed EDDR design for
ME testing can detect errors and recover data with an acceptable
area overhead and timing penalty. Importantly, the proposed
EDDR design performs satisfactorily in terms of throughput and
reliability for ME testing applications.
INTRODUCTION
ADVANCES in semiconductors, digital signal processing,
and communication technologies have made multimedia
applications more flexible and reliable. A good example is
the H.264 video standard, also known as MPEG-4 Part 10
Advanced Video Coding, which is widely regarded as the
next generation video compression standard [1], [2]. Video
compression is necessary in a wide range of applications to
reduce the total data amount required for transmitting or storing
video data. Among the coding systems, a ME is of priority
concern in exploiting the temporal redundancy between suc-
cessive frames, yet also the most time consuming aspect of
coding. Additionally, while performing up to 60%–90% of the
computations encountered in the entire coding system, a ME
is widely regarded as the most computationally intensive of a
video coding system [3].
PROPOSED EDDR ARCHITECTURE DESIGN
Fig. 1 shows the conceptual view of the proposed EDDR
scheme, which comprises two major circuit designs, i.e. error
detection circuit (EDC) and data recovery circuit (DRC), to de-
tect errors and recover the corresponding data in a specific CUT.
The test code generator (TCG) in Fig. 1 utilizes the concepts of
RQ code to generate the corresponding test codes for error de-
tection and data recovery. In other words, the test codes from
TCG and the primary output from CUT are delivered to EDC to
determine whether the CUT has errors. DRC is in charge of re-
covering data from TCG. Additionally, a selector is enabled to
export error-free data or data-recovery results. Importantly, an
array-based computing structure, such as ME, discrete cosine
transform (DCT), iterative logic array (ILA), and finite impulse
filter (FIR), is feasible for the proposed EDDR scheme to detect
errors and recover the corresponding data.
CONCLUSION
This work presents an EDDR architecture for detecting the
errors and recovering the data of PEs in a ME. Based on the
RQ code, a RQCG-based TCG design is developed to generate
the corresponding test codes to detect errors and recover data.
The proposed EDDR architecture is also implemented by using
VHDL and synthesized by the Synopsys Design Compiler with
TSMC 0.18- m 1P6M CMOS technology. Experimental results
indicate that that the proposed EDDR architecture can effec-
tively detect errors and recover data in PEs of a ME with reason-
able area overhead and only a slight time penalty. Throughput
and reliability issues are also discussed to demonstrate the satis-
factory performance of the proposed EDDR architecture design
for ME testing applications