03-11-2012, 01:40 PM
Digital Design Laboratory Assignment for Design and Implementation of a Digital Lock
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Purpose
The purpose of this lab is:
• 1. To design a finite state machine for a digital lock.
• 2. To learn to use HDL or the StateCAD editor to define a finite state machine.
• 3. To implement the finite state machine of the digital lock on a FPGA
• 4. Learn practical issues related to timing and testing of a synchronous FSM:
o generating a single synchronous input pulse when pressing a push-button
o synchronization of inputs
• 5. To experimentally check the operation of the lock
Problem statement and specifications
You need to design a digital lock that has three input push-buttons: A, B and C. Assume that the buttons cannot be pressed simultaneously (an electromechanical interlock guarantees this). The lock should have the following features:
1. When the combination B-C-A-C has been pressed, a signal UNLOCK is asserted that causes the lock to open.
2. Once the lock is open, one can close the lock by pressing any key.
3. To reset the lock to its initial state one can press the sequence A-A from any state, except the reset state or when the alarm has been activated.
4. In order to prevent tampering with the lock, an ALARM will go off after pressing a wrong button. However, in order to make it harder to figure out the right sequence, we don't want the alarm to go off after the first wrong button has been pressed. Instead, the alarm should go off after pressing 4 buttons, as long as one of the 4 buttons pressed is a wrong one (e.g. the sequences B-C-B-A, A-B-C-A, C-C-B-A, A-A-B-C, etc. would trigger the alarm).
Task one: Design of the Digital Lock FSM.
1. Make sure you understand the behavioral description of the project. As with any project specifications not all possibilities may be covered. Feel free to make reasonable assumptions and state them clearly.
2. Draw the State Diagram or State Machine Diagram (SMD) for the digital lock. If you make assumptions because not everything was specified, write them down. Indicate what each state represents, what input conditions cause the state transitions, and what the corresponding outputs are. Number the state S0, S1, etc. The digital lock should have as outputs the UNLOCK and ALARM signals. In order to follow the operation of the FSM during testing, you will also show in the 7-segment display the number of the state that is active. The state that corresponds to the UNLOCK and ALARM situation should be displayed as "U" and "A". It would be great is you could have the "A" blinking to draw the attention that the alarm has been set off. I would suggest to design the state diagram as a Moore machine since that makes the timing easier.
Task two: One-pulse circuit.
As part of this task you will be concentrating on implementing and testing your design. This raises some interesting issues which are mainly related to timing. In your design you have assumed that when you press the push-button it will generate a single pulse which is synchronized with the clock. In reality this is not going to be the case unless you take special precautions. We are concerned with three issues:
1. Pulse synchronization
2. Generation of a single pulse when pressing the button.
1. One of the complications comes from the fact that the switch will not close synchronously with the clock edge so as to ensure proper set-up and hold times for the flip-flops to which the input is connected. Synchronization can be easily ensured by passing the input signal through a clocked D flip-flop.