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Die singulation, also known as wafer dicing, is reviewed in terms of the brief history, critical
challenges, characterization of singulation quality, different singulation technologies and
underlying mechanisms, and post-singulation die strength enhancement. Mechanical blade dicing
has been the workhorse of die separation in the semiconductor manufacturing process. It faces
growing challenges due to the adoption of copper/low-k dielectric interconnect structures, thin and
ultra-thin wafers, die attach films, narrow dicing streets, and complex stacked structures on the dicing
streets. Key dicing quality characteristics are chipping, delamination, kerf geometry, die side
wall damage, die surface contamination, and die strength degradation. Various die singulation
technologies have been developed to address these challenges and quality issues, including dicing
by thinning, laser based approaches, laser and mechanical hybrid method, and plasma dicing. Die
strength is a critical parameter for thin and ultra-thin dies. Post-dicing die strength enhancement is
becoming the complement of most dicing technologies to achieve dies with high fracture strength.
Plasma dicing has the potential to achieve much higher die strengths than all the other dicing
approaches. VC 2012 American Vacuum Society. [http://dx.doi10.1116/1.3700230]
INTRODUCTION
Die singulation is also known as wafer dicing. It is a manufacturing
process to separate apart the individual dies on
a finished wafer via wafer dicing for further packaging and
assembly (Fig. 1). Today, die singulation has been used for
packaging and assembly of integrated semiconductor devices
[e.g., memory, processors, and radio frequency integrated
circuit (RFIC) devices], discrete semiconductor devices
[e.g., small-signal transistors and diodes, resistors, and light
emitting diodes (LEDs)], solar cells, and microelectromechanical
systems (MEMS).
Wafer dicing dates back to around 1955, with its first format
being scribing and breaking with diamond and later with
laser.1 During the 1960s and the 1970s, IBM used toothless
gang saws in SiC slurry to dice silicon wafers.2,3 In the early
1970s, diamond blade sawing was introduced as the second
format of wafer dicing. By 1983, fully automated in-line
blade sawing systems were introduced to the market.1 Over
the years, blade sawing has been the workhorse of wafer dicing
in the semiconductor manufacturing process, with continuous
improvement being made to address process
challenges and accommodate new design and application
requirements. Since the last decade, the mechanical dicing
approach has been facing many growing challenges from the
development in wafer fab and advanced packaging technologies,
emerging applications such as LEDs and MEMS, and
the more stringent yield-driven quality control. A variety of
new wafer dicing technologies have been developed to
address these tough challenges, particularly for thin and
ultrathin wafers.4 The early 2000s witnessed the emergence of several important dicing technologies: Laser ablation
based wafer dicing systems were offered to the industry for
dicing via full-thickness laser cutting5 or by hybrid laser
scribing/blade sawing.6 The dicing before grinding (DBG)
process7 and “stealth dicing,” a laser induced subsurface
separation technology,8 were also commercialized. Around
the same time, the idea of applying plasma etching for wafer
dicing was proposed.9 This contribution presents an extensive
review of die singulation processes with an emphasis on
the major challenges to wafer dicing, characterization of
dicing quality, various dicing technologies and post-dicing
die strength enhancement practice.
II. CHALLENGES TO DIE SINGULATION
A. Transition from Al/SiO2 to Cu/low-k interlayer
dielectric interconnect structures
Interconnects are charge carriers made of metal lines separated
by an insulating interlayer dielectric (ILD). Due to the
effective resistance ® and capacitance © of the interconnect
structures, the capacitive coupling of the metal lines to
the ILD produces the RC delay. The advanced ICs are driven
towards higher interconnect density and better interconnect
performance (lower RC delay) in support of increased function
integration and speed. Increasing interconnect density
can be achieved by increasing the number of metal layers
while shrinking interconnect dimensions. However, smaller
metal cross sections and reduced wire spacing lead to a significant
increase in R and C, causing a higher RC delay. In
addition, higher resistance also induces increased power consumption
and heat generation, reduced metal line spacing
causes more crosstalk.
As the interconnect structures transition from Al/SiO2
ILD to Cu/low-k ILD, the RC delay can be effectively
reduced due to the reduction of resistivity from aluminum
(Al, 2.65–2.82 lX-cm) to copper (Cu, 1.6 lX-cm) and that
of dielectric constant from SiO2 ILD (k ¼ 4.1) to low-k ILD
(k 3). The introduction of Cu also significantly reduces
power loss due to resistivity and improves the heat dissipation
due to thermal conductivity.11,12 The International
Technology Roadmap for Semiconductors (ITRS) has projected
the adoption of low-k ILDs matching with the technology
node shrinkage.13
The low-k materials have inherently weak thermomechanical
properties. The elastic modulus of low-k dielectrics
are typically below 10 GPa, while that of SiO2 is 70 GPa.
The coefficient of thermal expansion (CTE) of low-k films
are 10–17 ppm/K versus 0.6 ppm/K for SiO2.
12,14,15 Particularly,
the low-k films have very low fracture toughness
and poor adhesion to adjacent films in upper and lower
layers.14,16,17 This raises the concerns on the thermomechanical
integrity during fab processing, wafer dicing, die
packaging, and service. In fact, the poor adhesion induced
thin film delamination and cracking issue has been identified
as one of the key failure modes in chemical mechanical
polishing (CMP)14,17–20 and packaging processes, including
wafer dicing, die attach, wire bonding and molding. The
delamination and cracking driving forces can come from the
residual stresses within each layer, the thermal mismatch
stresses in the low-k stacks, the global thermal mismatch of
the package and the external loads.19–24
Also, copper is more ductile than aluminum and will
enhance the premature clogging of dicing blade, which adds
additional loading to the blade to cause excessive chipping.25
B. Thin wafers for thin dies
Dies for common microprocessor devices are typically
300 lm or thicker. Discrete devices (e.g., transistors, diodes,
LEDs), devices for IC cards and mobile products (e.g., memory,
logic, and microprocessors) have been moving rapidly
from 150–200 lm thickness range to 50–75 lm or even thinner
regime.
Basically, thin silicon dies enable two categories of applications:
three-dimensional (3D) ICs and systems-in-foil (SiF).26,27
Primarily, thin dies are needed to support 3D IC chip stacking
in system-in-package (SiP) solutions for continued miniaturization
and improved package functionality. In 3D system integration,
multiple active dies that bear active and lateral
interconnects as in the conventional planar ICs are vertically connected
via through silicon vias (TSVs). Minimizing chip thickness
will increase the planar TSV density by reducing TSV pitch
and via parasitics; thus increase the effectiveness of TSV interconnects.28
ITRS has projected the SiP technology trend with the
number of chips per SiP and Si wafer thickness requirement.13
Secondly, thin dies enable flexible electronics and display
development. Flexible electronics builds flip-chip packaging
and chip assembly on flexible substrates and on textiles and
therefore demands mechanically flexible chips,27–29 such as
contactless smart cards and radio frequency identification
(RFID) cards, biochips, and robot sensors/actuators.
Moreover, reducing wafer thickness improves heat dissipation
of dies.25,27
Thinner wafers are more flexible and tend to warp. Also, for
a given die strength value, a thinner die translates into a lower
value of allowable maximum load to avoid die fracture. This
implies that handling of thin dies becomes very challenging and
cannot simply follow the standard process steps for conventional
thick die placement.30,31 Schnegg et al. listed the challenges and
problems for thin die handling for die pickup, transfer and
placement processes. These challenges include die cracking, no
pickup, impact on neighboring die, die peel-off, ejection tool topography
design, slow ejection, die bending, die warpage, die
surface contamination, tool contamination, and poor recognition
quality in visual die alignment if die warpage causes illumination
issue.31 McCabe also pointed out the challenge to detach
large, thinned dies from the tape without cracking.32
In principle, the wafer thinning and dicing processes need
to be optimized to ensure that a thinner die has an even higher
strength than that for a regular thick die (i.e., to increase
cracking/fracture resistance of the die) so that it can tolerate a
relatively larger variation of the handling load during assembly.
On the other hand, the assembly tools and processes need
to be improved also in order to reduce the cracking/fracture
driving force to achieve tighter control over the handling load.