28-08-2014, 11:38 AM
An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. The program instructions written for embedded systems are referred to as firmware, and are stored in read-only memory or Flash memory chips. They run with limited computer hardware resources: little memory, small or non-existent keyboard or screen.
MICROCONTROLLER Microcontroller: Microcontroller can be termed as a single on chip computer which includes number of peripherals like RAM, EEPROM, Timers etc., required to perform some predefined task. Architecture of AVR Microcontroller There are number of popular families of microcontrollers which are used in different applications as per their capability and feasibility to perform the desired task, most common of these are 8051, AVR and PIC microcontrollers. ASSEMBLY PROGRAMMING LANGUAGE Assembly language is a low level programming language for computers, microprocessors, microcontrollers, and other programmable devices in which each statement corresponds to a single machine language instruction. An assembly language is specific to a certain computer architecture, in contrast to most high-level programming languages, which generally are portable to multiple systems. Assembly language programs are converted into executable machine code by a utility program referred to as an assembler, the conversion process being referred to as assembly or assembling the program. Assembly language uses mnemonics to represent the low-level machine operations that are unique to the target system. Depending on the particular instruction being assembled, an operand may be part of the instruction.. Generally speaking, there is a one–to–one correspondence between each assembly language statement and an executable machine instruction. An assembly language instruction consist of four fields: [label:] mnemonic [operands] [;comments] 8051 MICROCONTROLLER INTRODUCTION: Despite its relatively old age, the 8051 is one of the most popular microcontrollers in use today. Many derivative microcontrollers have since been developed that are based on--and compatible with--the 8051. Thus, the ability to program an 8051 is an important skill for anyone who plans to develop products that will take advantage of microcontrollers. PIN DESCRIPTION OF THE 805 1 ALE/PROG:- Address latch enable for latching the lower byte of address with a constant rate of 1/6th of oscillator frequency. This pin is also used for program pulse input during EEPROM programming. PSEN:- Program store enable is read strobe to external program memory. when the device is executing out of external program memory, PSEN is activated twice each machine cycle .PSEN is not activated when the device is executing out of internal program memory EA/VPP:-When EA is held high the CPU executes out of internal program memory. Holding EA low forces the CPU to execute out of external memory regardless of the program counter value. In the 80C31,EA must be externally wired low .In the EPROM devices ,this pin also receives the programming supply voltage during EPRPOM programming. RST:- It is an input and is active high upon applying a high pulse to this pin, The microcontroller will reset and terminate activities also named as power on RST. PORT 0:- Its 8 bit bidirectional port it can sink 8 TTL loads also used for multiplex low order address and data bus to external memory to which pull ups are required PORT 1:- Its an 8 bit bidirectional I/O port. It will source current due to internal pull-ups. PORT 2:- It emits high order address bite that used 16 bit addresses while emitting it uses strong pull-ups PORT 3:-Performs following functions P3.0 RxD(serial input port). P3.1 TxD(serial output port) P3.2 INT0(external interrupt 0). P3.3 INT1(external interrupt 1). P3.4T0(timer 0 external input). P3.5T1 timer 1 external input). P3.6 WR(external data memory write strobe). P3.7 RD external data memory read strobe). XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifier. VCC: Supply voltage. VSS: Circuit ground potential. MEMORY ORGANISATION :- The 8051 has three general types of memory. to effectively program the 8051 it is necessary to have a basic understanding of these memory types. The memory types are illustrated in the following graphic. They are: on chip memory, external code memory and external RAM on chip memory refer to any memory(code, ram or other) that physically exists on the microcontroller itself. External code memory is code memory that resides off-chip. This is often in the form of an external EPROM. this is often in the form of standard static RAM or flash RAM. CODE MEMORY:- code memory is the memory that hold the actual 8051 program that is to be run. This memory is limited to 64k and comes in many types and shapes code memory may be found on chips ,either burned into the microcontroller as ROM or EPROM. Code may also be stored completely off-chip in the external ROM or more commonly, An external EPROM .flash RAM is also another popular method of storing a program. When the program is stored on- chip the 64k maximum is often reduced to 4k,8k or 16k.this varies depending on the version of the chip that is being used . each version offers specific capabilities and one of the distinguishing factor from chip to chip is how much ROM/EPROM the chip has EXTERNAL RAM :- An obvious opposite internal ram. The 8051 also support what is called external ram As the name suggest , external ram is random access memory is found of chip. Since the memory is of chip it is not as flexible in terms of accessing and is also slower. For example ,to increment to an internal ram location by one require only one instructions and one instructions cycle to increment a one bit value stored in external ram required 4 instructions and 7 instructions cycle. In the case .external memory is 7 times slower. ON CHIP MEMORY:- As mentioned at the beginning of this chapter, The 8051 includes a certain amount of on-chip memory on-chip memory is really one of two types : Internal RAM and special function register memory. The layout of the 8051’s internal memory is presented in the memory map. The80 bytes remaining if the internal memory , from address 30h through 7fh, may used by user variable that need to be accessed frequently or at high-speed. This area is also utilized by the microcontroller as a storage area for the operating stack. This fact severally limits the 8051s stack since these 80 bytes has to be shared between the stack and user variables. INTERNAL RAM Register banks The 8051 uses 8 “R” registers which are used in many of its instructions . These “R” registers are numbered from 0 through 7 (R0,R1,R2,R3,R4,R5,R6and R7 ). The registers are generally used to assist in manipulating values and moving data from one memory location to another . for example , to add the value of R4 to the Accumulator, we would execute the following instruction: ADD A, R4 Thus if the accumulator (A) contained the value 6 and R4 contained the value 3 , the accumulator would contain the value 9 after this instruction was executed . But watch out ! As the memory map shows , the 8051 has four distinct register banks when the 8051is first booted up , register bank 0 (addresses 00h through 07h ) is used by default however , your program may instruct the 8051 to used by 1 of the alternate banks ; i.e., register banks 1,2 or 3. In this case R4 wall no longer be the same as internal RAM address 04h. BIT MEMORY The 8051 , being a communications – oriented micro controller , gives the use ability to access a number of bit variables . These variables may be either one or There are 128 bit variables available to the user , numbered 00h through 7FH. The user may use of these variables with commands such as SETB and CLR . For example , to sit bit number 24 (hex) to one you would execute the instruction SETB 24h It is important to note Bit Memory is really a part of internal RAM . In fact, the 128 bit variables occupy the 16 bytes of internal RAM from 20h through 2Fh. SPECIAL FUNCTION REGISTER A Map of the on chip memory area called the special function register (S F R ) space is shown in figure 1.5 note that the SFRs not all of the addresses are occupied . un occupied addresses are not implemented on the chip . read accesses to these addresses will in general return random data , and write accesses will have no effect . user software should not write is to these unimplemented location , since they may be used in other 80c51 family derivative products to invoke new features. The functions of the SFRs are described: Accumulator: ACC is the Accumulator register. The mnemonics for accumulator _ specific instructions however, refer to the accumulator simply as A . B Register: The B register is used during multiply and divide operations . for other instructions it can be treated as another scratch pad register. Program status word : Program status word: The program status word (PSW) contains several status bits that reflect the current state of CPU . the PSW shown in figure 1.1, reside in the SFR space. It contains the carry bit, and two user definable status flags. The carry bits, other than severing the function of a carry bit in arithmetic operation also serve as the banks. A number of instruction refers to these RAM location as R0 through R7. The selection of which is the four is being refered to is made on the RS0 and RSI at execution time. The parity bit reflect the number of 1s in the accumulator: P=1 if the accumulator contain an odd number of 1s,P-0 if the accumulator contains an even number of 1s. thus the number of 1s in the accumulator pulse is always even. Two bits in the PSW are uncommited and may be used as general purpose status flag. Stack pointer: The stack pointer register is 8bits wide. It is incremented before data is stored during PUSH and call excution. While the stack may reside anywhere in on-chip RAM, the stack pointer is intialized to 07H after a reset. This couse the stack to begine tat location 08H. Data pointer: The data pointer consite of high bytr(DPH) and low byte(DPL). Its intended function is hold a 16-bit address. It may be mnipulate as a16-bit register or as two indepented 8_bit registers. Ports 0to 3 P0,P1.P2 and P3 are the SFR latches of port 0,1,2 and 3 respectively. Wiriting a one to a bit of a port SFR (P0,P1,P2 or P3) cause the corresponding port output pin to switch high. Writing a zero cause the port output pin to switch low. Wheen used as a input, the extarnal state of a port pin will be hed in the port SFR(I.e if the extarnal state lof a pin is low, the corresponding port SSFR bit caintine a0:if it is high, the bit will contain a1). Serial data Buffer: The serial buffer is actullay two seprate registers, a transmit buffer and a receive buffer. When the data is moved to SBUF , it goes to the transmit buffer and is held gor derial transmission. Timer registers: Register pair (TH0,TL0) and (TH1,TL1) are the 16 bit counting registers for timer/ counter 0 and 1 respectively. Control Register: Special function registers IP’IE,TMOD,SCON,PCOn containcontrol and status bits for the interrupt system, the timer/counter, and the serial port. They describe in later section. Machine Cycle: The CPU takes a certain nuber of clock cycle to execute an instruction. These clock cycles are know as machine cycle. Crystal Frequency- It is the frequency produce by the crystal oscillator connect to microcontroller. Typical values used are 11.0592MHz and 12MHZ. 1 Machine cycle= crystall frequency/12 RISC/CISC Architecture- Microprosseor use two type of architecture, namely as RISC and CISC. These may be defined as- Complex Instruction Set Computing (CISC)- The microprocessor using CISC architecture have many instruction into it. This saves the processing time for performing task. The time saved because the required instruction are available in the microprocessor itself and it does not have to retrieve the instruction from the program stored in the external memory such as the RAM. However, the instruction built into the microprocessor affects the performance of the microproccesor. This is becouse more time is taken to process the instruction and also the space available an the the microprosessor for processing reduce. To overcome this problem more transistors need to bee built into the microprocessor to maintain the speed of microprocessor. Reduced Instruction Set Computing (RISC)- The microprocessor using RISC architecture have limited instruction built into it. This requires few transistor to be built into microprocessor to makeup for the time delay in processing this instruction. The reduction in instruction also saves the space in the microprocessor. The RISC microprocessor is cheaper to build thsn the CISC processor. Addressing Mode An addressing mode reffers to how you are addressing a given memory location. In summary, the addressing mode are as follows, with an example of each: Immediate addressing MOV A,#20h Direct addressing MOV A,30h Indirect Addressing MOV A,@R0 External direct MOVX A,@A+DPTR Code Indirect MOVC A,@A=DPTR Instruction Set: Depending on operation they perform, all instruction are divided in several group: • Arithmetic Instruction • Branch instruction • Data transfer instruction • Logic instruction • Bit-oriented instruction • INC R1- means: increment register R1 ( increment register R1) • LJMP LAB5- means: long jump LAB5 (long jump to the address marked as LAB5) • JNZ LOOP – means: jump if not zero loop • RET- returns from a subroutine • JZ TEMP – if the number in the accumulator is not 0 jump to the address marks TEMP • ADD A,R3 add R3 and accumulator • CJNE A,#20,LOOP- compare accumulator with 20. If they are not equal, jump to the address marked as LOOP. ARITHMETIC INSTRUCTIONS Mnemonic Description Byte Cycle ADD A ,Rn Adds the register to the accumulator 1 1 ADD A, direct Adds the direct byte to the accumulator 2 2 ADD A, @Ri Adds the indirect Ram to the accumulator 1 2 ADD A, #data Adds the immediate data to the accumulator 2 2 ADDC A, Rn Adds the register to the accumulator with a carry flag 1 1 ADDC A, direct Adds the direct byte to the accumulator with a carry flag 2 2 ADDC A, @Ri Adds the indirect RAM to the accumulator with a carry flag 1 2 ADDC A, #data Adds the immediate data to the accumulator with a carry flag 2 2 SUBB A, Rn Subtracts the registered from the accumulator with a borrow 1 1 SUBB A ,direct Subtracts the direct byte from to the accumulator with a borrow 2 2 SUBB A, @ri Subtracts the indirect RAM from the accumulator with a borrow 1 2 SUBB A, #data Subtracts the immediate data from the accumulator with a borrow 2 2 INC A Increments the accumulator by 1 1 1 INC Rn Increments the register by I 1 2 INC Rx Increments the direct byte by 1 2 3 INC @Ri Increments the indirect RAM by 1 1 3 DEC A Decrements the accumulator by 1 1 1 DEC Rn Decrements the register by 1 1 1 DEC Rx Decrement the direct byte by 1 1 2 DEC @Ri Decrement the indirect RAM by 1 2 3 INC DPTR Increments the data pointer by 1 1 3 MUL AB Multiplies A and B 1 5 DIV AB Divides A by B 1 5 DA A Decimal adjustment of the accumulator according to BCD code 1 1 Branch Instructions;- There are two kinds of branch instructions; Unconditional jump instructions; upon their execution a jump to a new location from where execution is executed. Conditional jump instructions; a jump to a new program location is executed only if a specified condition is met. Otherwise,the program normally proceeds with the next instruction. BRANCH INSTRUCTION Mnemonic Description Byte Cycle ACLL addr 11 Absolute subroutine call 2 6 LCALL addr 16 Long subroutine call 3 6 RET Returns from subroutine 1 4 RETI Returns from interrupt subroutine 1 4 AJMP addr 11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (from-128to +127 location relative to following instruction 2 3 JC rel Jump if carry flag is set Short jump 2 3 JNC rel Jump if carry flag is not set short jump 2 3 JB bit , rel Jump if direct bit is set short jump 3 4 JBC bit, rel Jump if direct bit is set and clears bit short jump 3 4 JMP @A+dptr Jump indirect relative to the DPTR 1 2 JZ rel Jump if the accumulator is zero. Shot jump 2 3 JNZ rel Jump if the accumulator is not zero . Short jump 2 3 CJNE A, direct,rel Compares direct byte the accumulator and jumps if not equal . Short jump 3 4 CJNE A, #data,rel Compares immediate data to the accumulator and jump if not equal short jump 3 4 CJN RN ,#data rel Compares immediate data to the register and jump if not equal short jump 3 4 CJNE@RI,#data,rel Compares immediate data to indirect register and jumps if not equal Short jump 3 4 DJNZ Rn,rel Decrements register and jumps if not 0, Short jump 2 3 DJNZ Rx,rel Decrements direct byte and jump if not 0. Short jump 3 4 NOP No operation 1 1 Data transfer instructions Data transfer instructions move the contents of one register to another. The register the content of which is moved remains unchanged. If they have suffix x (MOVX),the data is exchanged with external memory Mnemonic Description byte Cycle MOV A,Rn Moves the reg. To accumulator 1 1 MOV A,direct Moves direct byte to accumulator 2 2 MOV A,@Ri Moves indirect RAM to accumulator 1 2 MOV A,#data Moves immediate data to accumulator 2 2 MOV Rn, A Moves accumulator to the register 1 2 MOV Rn, direct Moves direct byte to the register 2 4 MOV Rn, #data Moves immediate data to register 2 2 MOV direct, A Moves accumulator to direct byte 2 3 MOV direct,Rn Moves register to direct byte 2 3 MOV direct,direct Moves direct byte to direct byte. 3 4 MOV direct,@Ri Moves indirect RAM to direct byte 2 4 MOV direct,#data Moves immediate data to direct byte 3 3 MOV @Ri,A Moves accumulator to indirect RAM 1 3 MOV @Ri,direct Moves direct byte to indirect RAM 2 5 MOV @Ri,#data Moves immediate data to indirect RAM 2 3 MOV DPTR,#data Moves 16 bits data to data pointer 3 3 MOVC A,@A+DPTR Moves code byte relative to the DPTR to accumulator 1 3 MOVC A,@A+PC Moves code byte relative to the PC to the accumulator 1 3 MOVX A,@Ri Moves the external RAM to the accumulator (8 bit address) 1 3-10 MOVX A,@DPTR Moves the external RAM to the accumulator (16 bit address) 1 3-10 MOVX,@Ri, A Moves accumulator to the external RAM (8 BIT) 1 4-11 MOVX @DPTR,A Moves accumulator to the external RAM (16 BIT) 1 4-11 PUSH direct Push direct byte onto stack 2 4 POP direct Pops direct byte from the stack 2 3 XCH A,Rn Exchanges the register with the accumulator. 1 2 XCH A,direct Exchanges the direct byte with the accumulator. 2 3 XCH A,@ Ri Exchanges the indirect RAM with the accumulator 1 3 XCHD A,@Ri Exchanges the low order nibble indirect RAM with the accumulator 1 3 Logic instruction Logic instruction perform logic operations upon corresponding bits of two register . LOGIC INSTRUCTION Mnemonic Description Byte Cycle ANL AND register to accumulator 1 1 ANL AND direct byte to accumulator 2 2 ANL AND indirect RAM to accumulator 1 2 ANL AND immediate data to accumulator 2 2 ANL AND accumulator to direct byte 2 3 ANL AND immediate data to direct register 3 4 ORL OR register to accumulator 1 1 ORL OR direct byte to accumulator 2 2 ORL OR indirect RAM to accumulator 1 2 ORL OR accumulator to direct byte 2 3 ORL OR immediate data to direct byte 3 4 XRL Exclusive OR register to accumulator 1 1 XRL Exclusive OR direct byte to accumulator 2 2 XRL Exclusive OR indirect RAM to accumulator 1 2 XRL Exclusive OR immediate data accumulator 2 2 XRL Exclusive Or accumulator to direct byte 2 3 XORL direct, data Exclusive OR immediate data to direct byte 3 4 CLR A Clear to accumulator 1 1 CPL A Complements the accumulator (1=0-0=1) 1 1 SWAP A Swap nibbles with in the accumulator 1 1 RLC A Rotate bits in the accumulator left 1 1 RLC A Rotate bits in the accumulator left through carry 1 1 RR A Rotate bits in the accumulator right 1 1 RRC A Rotate bits in the accumulator right through carry 1 1 TIMER/COUNTERS: MCS-51 has two 16 bit timer/ Counter register. Timer 0 and timer 1. Both can be configured to operate either as timer or event counter. In the timer function the register is increment every machine cycle. Timer/ Counters Mode Control (TMOD) register TIMER 1 TIMER 2 GATE C/T M1 M0 GATE C/T M1 M0 GATE: Gating control when set. Timer/counter X is enabled only while INTx pin is high and TRx control pin is set C/T: Timer or counter selector cleared for timer operation and set for counter operation M1 M0 Operating 0 0 8048 timer, Tlx serves as 5 bit presales 0 1 16 bit timer/ counter THx and TLx are cascaded, there is no presales 1 0 8 bit auto reload timer/counter THx hold a value which is tube reloaded into Tlx each time it overflows 1 1 (Timer 0) TL0 is an 8 bit timer/ counter controlled by standard timer 0 control bitstimer 1) timer/ counter 1 stopped Timer/counter control(TCON) Register MSB LSB TF1 TR1 TF0 TF1 TR1 TF0 TF1 TR1 BIT SYMBOL Function TCON.7 TF1 Timer 1 overflow flag. Set by hardware on timer/ counter overflow. Cleared by hard ware when processor vector to interrupt or clearing the bit in software. TCON.6 TR1 Timer 1 run control bit. Set /cleared by software to turn timer/counter on/off TCON.5 TF0 Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vector to interrupt routine, or clearing the bit in software TCON.4 TR0 Timer 1 run control bit, set/ cleared by software to turn timer/ counter on/off TCON.3 IE1 Interrupt 1 edge flag. Set/cleared by hardware when external interrupt edge detected. Cleared when interrupt processed TCON.2 IT1 Interrupt 1 type control bit. Set/ cleared by software to specify falling edge/ low level triggered external interrupt TCON.1 IE0 Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed TCON.0 IT0 Interrupt 0 type control bit. Set/ cleared by software to specify falling edge/low level triggered external interrupts. SERIAL COMMUNICATION One of the 8051s many powerful features is its integrated UART, otherwise known as a serial port. The fact that the 8051 has an integrated serial port means that you may very easily read and with value to the serial port. If it were not for the integrated serial port, writing a byte to a byte toe a serial line would be rather tedious process requiring turning on and off one of the I/O line in rapid succession to properly clock out each individual bit , including start bits, stop bits and parity bits. However , we do not have to do this . instead , we simply need to configure the serial port or read the same SFR to read a value from the serial port. The 8051 will automatically let us know when it has finished sending the character we wrote and will also let us know whenever it has received a byte so that we can process it . we do not have to worry about transmission at level—which saves us quite a bit of coding and processing time. Setting the serial port Mode: The first thing we must do when using the 8051s integrated serial port is , obviously, configure it. This let us tell the 8051 how many data bits we want the baud rate we will be using, and how the baud rate will be determine. Setting the Baud Rate: The baud rate in 8051 is programmable and it is done with the help of timer 1. There are many baud rate used in 8051 like 1200,2400,4800,9600 etc. this set by planning the value in TH1 Bit Name Bit Address Explanation of function 7 SM0 9FH Serial port mode bit 0 6 SM1 9EH Serial port mode bit 1 5 SM2 9DH Multiprocessor communication enable 4 REN 9CH Receiver enable this bit must be set in order to receive character. 3 TB8 9BH Transmit bit 8. The 9th bit to transmit in mode 2 and 3 2 RB8 9AH Receive bit 8 . the 9th bit received in mode 2 and 3 1 T1 99H Transmit flag. Set when a byte has been completely transmitted. 0 R1 98H Receive flag. Set when a byte has been completely Additionally,it is necessary to define the function of SM0 and SM1 by an additional table. SM0 SM1 Serial mode explanation Baud rate 0 0 0 8-bit shift register Oscillator/12 0 1 1 8-bit UART Set by timer 1(*) 1 0 2 9-bit UART Oscillator/32(*) 1 1 3 9-bit UART Set by timer1(*) The baud rate indicated in this table is doubled if PCON.7(SMOD) is set. Following are the steps used to serially transmit a byte to serial port- 1) Program timer one (TI) for mode 2(TMOD=20h) 2) Load TH1 with some value to set baud rate. 3) Program SCON for mode 1(SCON=50h). 4) Start timer one (T1) 5) Clear T1 6) Load SBUF with the byte to be transmitted. 7) Moniter the T1 flag bit until it becomes one using it becomes one using instruction “JNB T1,XX”. 8) go back to step 5 for next byte. INTERRUPTS Types of interrupts 1) Level triggered- In this mode, when a low level signal is applied to INT0 and INT1 then the microcontroller triggers the interrupt. after that controller stops whatever it is doing and jumps to interrupt vector table to service the interrupt 2) Edge triggered-Upon reset INT0 and INT1 are lower level triggered. for making them edge triggered IT0 and IT1 bits of TCON register are programmed .when these bits are made high then interrupts become edge triggered The 80C51 provides 5 interrupt sources. these are shown in the table .the external interruptsINT0 and INT1can each be either level activated, depending on bits IT0 and IT1 can each be either level activated or transition activated or depending on bits IT0 and IT1 in register TCON .the flags that actually generate these interrupts are bits IE0 and IE1 in TCON .when an external interrupt is generate, the flag that generated it is cleared by the hardware. Interrupt Interrupt flag Interrupt flag address External 0 IE0 000 3h Timer0 TF0 000 Bh External 1 IE1 001 3h Timer1 TF1 001 Bh Serial R1/T1 002 3h The timer 0 and timer 1interrupts are generated by TF0 and TF1 which are set-up by a rollover in their respective timer /counter register. when a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to . the serial port interrupt is generated by the logical OR of RI and TI. Interrupt Enable Register:- To enable an interrupt ,IE registers must be programmed. following tables show the bits of IE registered and their functions Bit Symbol Function IE.7 EA Disables all interrupt. if EA =0,no interrupt will be acknowledge. if EA=1,each interrupt sources is individually enabled and disabled by setting or clearing its enable bit IE.6 - Reserved IE.5 - Reserved IE.4 ES Enabled or disabled the serial port interrupt if EA=0,the serial port interrupt is disabled IE.3 ET1 Enabled or disabled the timer 1 over flow interrupt. if ET1 =0,the timer 1 interrupt is disabled IE.2 EX1 Enabled or disabled external interrupt 1.if EX=0 external interrupt is disable IE.1 ET0 Enabled or disabled the timer 0 or flow interrupt if ET=0 the timer 0 interrupt is disabled IE.0 EX0 Enabled or disabled external interrupt 0.if EX=0 external interrupt is disable All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. that is interrupt can be generated or pending interrupts can be canceled in software. each of these sources can be individual enable or disabled by setting or clearing a bit in special function register IE.IE also contains a global bit, EA which disables all interrupt at once Steps in executing an interrupt- 1) The microcontroller finishes the current instruction it is executing & saves the address of next instruction on the stack 2) It also saves the current status of all interrupts internally 3) It jumps to a fixed location in the memory at address given in the interrupt vector table 4) Upon executing RETI instruction, the microcontroller returns to the place where it was interrupted. INTERFACINGS +5V power supply. Interfacing switch to microcontroller 8051. Fig. show interfacing to port 0 or any pin to be used as a input pin is kept as HIGH. Otherwise it will be read as LOW by default .when the switch is not pressed the 10k register provides current needed for logic one. Closer of switch provides logic 0 to the controller PIN Interfacing LED to microcontroller:- In fig. anode is connected to a register to Vcc and cathode is connected to controller pin so when this pin is high, LED is OFF and when pin in LOW ,LED is ON . Interfacing 7-seg display to microcontroller :- These are basically 7 LED’s. 2 types are there :- Common anode where all segment share the same anode Common cathode where all segment share the same cathode . In common anode in order to turn ON ,segment corresponding pin must be set to 0 and 1 to OFF. Interfacing ADC 0808 to 8051:- In lot of embedded systems controller needs to take analog input .most of sensors and transducers such as temperature, humidity, pressure are analog. For interfacing these sensors to microcontroller we require to convert the analog output of these sensors to digital so that the controller can read it. Some microcontroller have built in analog to digital converter so there is no need of external ADC. For microcontroller that don’t have internal ADC external ADC is used. AVR MICROCONTROLLER History of AVR: AVR was developed in the year 1996 by Atmel Corporation. The architecture of AVR was developed by Alf-Egil Bogen and Vegard Wollan. AVR derives its name from its developers and stands for Alf-Egil Bogen Vegard Wollan RISC microcontroller, also known as Advanced Virtual RISC. The AT90S8515 was the first microcontroller which was based on AVR architecture however the first microcontroller to hit the commercial market was AT90S1200 in the year 1997. AVR microcontrollers are available in three categories: 1. TinyAVR – Less memory, small size, suitable only for simpler applications 2. MegaAVR – These are the most popular ones having good amount of memory (upto 256 KB), higher number of inbuilt peripherals and suitable for moderate to complex applications. 3. XmegaAVR – Used commercially for complex applications, which require large program memory and high speed. The following table compares the above mentioned AVR series of microcontrollers: Series Name Pins Flash Memory Special Feature TinyAVR 6-32 0.5-8 KB Small in size MegaAVR 28-100 4-256KB Extended peripherals XmegaAVR 44-100 16-384KB DMA , Event System included IMPORTANCE OF AVR: They are fast: AVR microcontroller executes most of the instructions in single execution cycle. AVRs are about 4 times faster than PICs, they consume less power and can be operated in different power saving modes. Let’s do the comparison between the three most commonly used families of microcontrollers. 8051 PIC AVR SPEED Slow Moderate Fast MEMORY Small Large Large ARCHITECTURE CISC RISC RISC ADC Not Present Inbuilt Inbuilt Timers Inbuilt Inbuilt Inbuilt PWM Channels Not Present Inbuilt Inbuilt AVR is an 8-bit microcontroller belonging to the family of Reduced Instruction Set Computer (RISC). In RISC architecture the instruction set of the computer are not only fewer in number but also simpler and faster in operation. The other type of categorization is CISC (Complex Instruction Set Computers). The Performance Equation: The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. Architecture of AVR The AVR microcontrollers are based on the advanced RISC architecture and consist of 32 x 8-bit general purpose working registers. Within one single clock cycle, AVR can take inputs from two general purpose registers and put them to ALU for carrying out the requested operation, and transfer back the result to an arbitrary register. The ALU can perform arithmetic as well as logical operations over the inputs from the register or between the register and a constant. Single register operations like taking a complement can also be executed in ALU. We can see that AVR does not have any register like accumulator as in 8051 family of microcontrollers; the operations can be performed between any of the registers and can be stored in either of them. AVR follows Harvard Architecture format in which the processor is equipped with separate memories and buses for Program and the Data information. Here while an instruction is being executed, the next instruction is pre-fetched from the program memory. Since AVR can perform single cycle execution, it means that AVR can execute 1 million instructions per second if cycle frequency is 1MHz. The higher is the operating frequency of the controller, the higher will be its processing speed. We need to optimize the power consumption with processing speed and hence need to select the operating frequency accordingly. There are two flavors for Atmega8515 microcontroller: 1. Atmega8515:- Operating frequency range is 0 – 16 MHz and operating voltage range is 4.5V to 5.5V 2. Atmega8515L:- Operating frequency range is 0 – 8 MHz and operating voltage range is 2.7V to 5.5V If we are using a crystal of 8 MHz = 8 x 106 Hertz = 8 Million cycles, then AVR can execute 8 million instructions. Naming Convention.! The AT refers to Atmel the manufacturer, Mega means that the microcontroller belong to MegaAVR category,8 signifies the memory of the controller, which is 16KB. • The pin diagram of Atmega8 microcontroller:- Pin Diagram - Atmega8 Memory: It has 8 Kb of Flash program memory (10,000 Write/Erase cycles durability), 512 Bytes of EEPROM (100,000 Write/Erase Cycles). 1Kbyte Internal SRAM I/O Ports: 35 I/ line can be obtained from three ports; namely Port A,Port B, Port C ,Port D and Port D. Interrupts: Two External Interrupt source, located at port D. 19 different interrupt vectors supporting 19 events generated by internal peripherals. Timer/Counter: Three Internal Timers are available, two 8 bit, one 16 bit, offering various operating modes and supporting internal or external clocking. SPI (Serial Peripheral interface): ATmega8 holds three communication devices integrated. One of them is Serial Peripheral Interface. Four pins are assigned to Atmega8 to implement this scheme of communication. USART: One of the most powerful communication solutions is USART and ATmega8 supports both synchronous and asynchronous data transfer schemes. It has three pins assigned for that. In many projects, this module is extensively used for PC-Micro controller communication. Analog Comparator: A comparator module is integrated in the IC that provides comparison facility between two voltages connected to the two inputs of the Analog comparator via External pins attached to the micro controller. Analog to Digital Converter: Inbuilt analog to digital converter can convert an analog input signal into digital data of 10bit resolution. For most of the low end application, this much resolution is enough. THE INTERNAL ARCHITECTURE BLOCK DIAGRAM OF ATMEGA8 HARDWARE:INTERFACINGS DONE WITH MICROCONTROLLERS 1. RESET AND OSCILLATORY CIRCUITRY: 2. LED INTERFACING TO 8051 MICROCONTROLLER: 3. RELAY SWITCH INTERFACING TO MICROCONTROLLER 8051: 4. INTERFACING MAX232 TO 8051 MICROCONTROLLER FOR SERIAL COMMUNICATION: 5. INTERFACING LCD TO 8051 MICROCONTROLLER: 6. INTERFACING STEPPER MOTOR TO 8051 MICROCONTROLLER: 7. INTERFACING ADC TO 8051 MICROCNTROLLER: 8. INTERFACING KEYPAD TO 8051 MICROCONTROLLER: PCB DESIGNING: Printed Circuit Board(PCB): Printed Circuit Board is an Electronic Board that connects circuit components.PCB populated with electronic components is a printed circuit assembly (PCA).PCBs are rugged, inexpensive, and can be highly reliable.Mass manufacturing is possible Materials of PCB: Conducting layers are typically made of thin copper foil. The board is typically coated with a solder mask that is green in color. Other colors that is normally available is blue. Unwanted copper is removed from the substrate after etching leaving only the desired copper traces or pathways Parts of a PCB: 1. Components: Components are the actual devices used in the circuit.This includes input/output connections. I/O ports, including power supply connections, are also important in the PCB design. 2. Pads: Location that components connect to.You will solder components to the pads on the PCB. Pads will connect to traces.Pads have an inner diameter and outer diameter. 3. Traces: Traces connect pads together.Traces are essentially the wiring of the PCB.Equivalent to wire for conducting signals.Traces sometimes connect to vias.High current traces should be wide.Signal traces usually narrower than power or ground traces. 4. Vias : Pad with a plated hole connecting traces from one layer of board to other layers.Attempt to minimize via use in your PCBs. Some component leads can be used as vias. 5. Top Layer: Most of the components reside on the top layer.Fewer traces on the top layer.Components are soldered to the pads on the top layer of PCB .Higher circuit densities 6. Bottom Layer: Few components on this layer.Many traces on this layer.Most soldering done on this layer. Jumper: Often, many signal wires need to exist in too small of a space and must overlap. Running traces on different PCB layers is an option. Multilayer PCBs are often expensive. Solution: use jumpers Solder Mask: Protect copper traces on outer layers from corrosion Areas that shouldn't be soldered may be covered with polymer resist solder mask coating Designed to keep solder only in certain areas Prevents solder form binding between conductors and thereby creating short circuits Silkscreen: Printing on the solder mask to designate component locations Readable information about component part numbers and placement. Helpful in assembling, testing and servicing the circuit board. Multilayer PCBs: More then a top and bottom layer. Typically there will be a power plane, ground plane, top layer, and bottom layer. Sometimes signal layers are added as needed. Sometimes RF planes made of more expensive materials are added. Physical Design Issues: 1. Component Size: Make sure components will actually fit.This especially applies for circuits that require high component densities.Some components come in multiple sizes. SMT vs Through Hole.Sometimes you can get tall and narrow caps or short and wide capacitors. 2. Heat Dissipation: Heat sink dissipates heat off the component.Doesn’t remove the heat just moves it.Some components may get hot. Make sure you get a large enough heat sink.Data sheets specify the size of the heat sink.A short circuit may result when two devices share the same heat sink 3. Mounting Points: The PCB needs to be mechanically secured to something.Could be the chassis-consist of metal frame on which the circuit boards and other electronic components are mounted.Could be another PCB/socket on PCB.Could be attachments to a heatsink. Parasitics: Series Inductance: Not an issue for low frequency circuits(<10 Mhz) The inductance of a trace may be signifigant. For power connections, a shunt capacitor is added to counter the series inductance of a long trace. A capacitor has a low AC impedance source A 100nF capacitor is often used along with a larger capacitor. 100 nF ceramics have very low impedance at higher frequencies. Shunt Capacitance: Result of wide wires over a ground plane. Limits speed of circuits, including digital circuits Typically insignificant for low performance circuits. To minimize place a capacitor from voltage to ground Inductive Coupling: Transfer of energy from one circuit component to another through shared magnetic field Change in current flow through one device induces current flow in other device Current flow in one trace induces current in another trace Minimize the long parallel runs of traces Run traces perpendicular to each other Capacitive Coupling: Transfer of energy in electrical n/w due to capacitance between circuit nodes Minimizing long traces on adjacent layers will reduce capacitive coupling Ground planes are run between the signals that might affect each other. Steps in PCB design: 1. Film Generation 2. Shear Raw Material 3. Drill Holes 4. Electrolus copper: Apply copper in hole barrels 5. Apply Image: Apply Photosensitive Material to develop selected areas from panel • 6. Strip and Etch: Remove dryfilm, then etch exposed copper 7. Solder Mask: Apply solder mask area to entire board with the exception of solder pads 8. Solder Coat: Apply solder to pads 9. Silkscreen: Apply white letter marking using screen printing process ARM MICROCONTROLLER ARM core dataflow model: Registers: Generic Program Status Register: Processor Modes: • The ARM has six operating modes: – User (unprivileged mode under which most tasks run) (10000) – FIQ (p) (entered when a high priority (fast) interrupt is raised) (10001) – IRQ (p) (entered when a low priority (normal) interrupt is raised) (10010) – Supervisor (p) (entered after reset and and is generally the mode that an os kernel operates in) (10011) – Abort ( p) (used to handle memory access violations) (10111) – Undef ( p) (used to handle undefined instructions) (11011) • ARM Architecture Version 4 adds a seventh mode: – System (p) (privileged mode using the same registers as user mode) (11111) Privileged mode allows full read-write access to CPSR. Nonprivileged only allows read access to the control field but still allows read-write access to the condition flags. State and Instruction set: Two instruction sets :- i) ARM ii) Thumb (T bit in cpsr is 1) • To change states the core executes a specialized branch instructions. • Jazelle ( cpsr T=0 ,J=1) Instruction size is 8-bit . To execute java bytecode , we require the Jazelle technology plus a specially modified version of Java virtual machine. ARM & Thumb instruction set features: ARM (cpsr T-0) Thumb (cpsr T=1) Instruction size 32-bit 16-bit Core instructions 58 30 Conditional execution Most Only branch instructions Data Processing instruction Access to barrel shifter and ALU Separate barrel shifter and ALU instructions Program status register Read-write in privileged mode No direct access Register usage 15 general purpose register +pc 8 general purpose registers +7 high registers +pc Exceptions& Interrupts: • Reset Vector – is the location of the instruction executed by the processor when power is applied.Instruction branches to initialization code. • Undefined Instruction Vector -- is used when the processor cannot decode an instruction. • Software interrupt Vector--- is called when you execute a SWI . The SWI instruction is frequently used as the mechanism to invoke an OS routine. • Prefetch Abort Vector --- occurs when the processor attempts to fetch an instruction from an address without the correct access permissions. The actual abort occurs in the decode stage. • Data abort Vector--- is similar to a prefetch abort but is raised when an instruction attempts to access data memory w/o the correct access permissions. • Interrupt request vector --- is used by external hardware to interrupt the normal execution flow of the processor. It can only be raised if IRQs are not masked in the cpsr. • FIQ vector- is used for hardware requiring faster response time. It can only be raised if IRQs are not masked in the cpsr. Core extensions: • Hardware extensions are standard components placed next to the ARM core. • Improve performance • Manage resources • Provide extra functionality • Provide flexibility in handling particular applications There are three hardware extensions ARM wraps around the core :- 1) Cache and Tightly coupled memory 2) Memory Management 3) Coprocessor Interface Cache and tightly coupled memory: Cache is a block of fast memory placed between main memory and core.Caches are used to improve the overall system performance. • Von Neumann-style • Harvard-style Cache provides an overall increase in performance but at the expense of predictable execution. Tightly Coupled Memory: TCMs are used to improve deterministic real-time response. It is a fast SRAM located close to core and guarantees the clock cycle required to fetch instructions or data – critical for real-time algorithms requiring deterministic behavior.By combining both technologies, ARM processors can have both improved performance and predictable real-time response. Memory management Used to organize memory and protect system resources.Three different types of memory management H/W 1) Nonprotected memory 2) Memory protection unit (MPU) 3) Memory Management Unit (MMU ) Non Protected Memory: No extensions providing no protection.Used for small, simple embedded that require no protection from applications Memory Protection Unit: Memory protection unit (MPU) uses a limited number of memory regions, these regions are controlled with a set of special coprocessor registers , & each region is defined with specific access permissions. This type of memory management is used for systems that require memory protection but don’t have complex memory map. Memory Management Unit: Most comprehensive memory management .Uses a set of translation table to provide fine-grained control over memory.These tables are stored in main memory and provide a virtual –to- physical address map as well as access permissions.MMU s are designed for more sophisticated platform operating systems that support multitasking. Coprocessors Extends the processing features of a core by extending the instruction set or by providing configuration registers .More than one coprocessor can be added to the ARM core via the coprocessor interface .The coprocessor can be accesses through a group of dedicated ARM instructions that provide a load –store type interface .Example: coprocessor 15 which controls the cache, TCM, and memory management. Coprocessor can also extend the instruction set by providing a specialized group of new instructions .Example: Set on instruction to perform vector floating –point (VFP) operations .The new instructions are processed in the decode stage of ARM pipeline .If the decode stage sees a coprocessor instruction , then it offers it to the relevant coprocessor .If coprocessor is not present then ARM takes an undefined instruction exception. Which allows us to emulate the behavior of the coprocessor in software. Main features of the ARM Instruction Set: • All instructions are 32 bits long. • Most instructions execute in a single cycle. • Every instruction can be conditionally executed. • A load/store architecture – Data processing instructions act only on registers • Three operand format • Combined ALU and shifter for high speed bit manipulation – Specific memory access instructions with powerful auto-indexing addressing modes. • 32 bit and 8 bit data types and also 16 bit data types on ARM Architecture v4. • Flexible multiple register load and store instructions • Instruction set extension via coprocessors ARM architecture: • Architecture version – Version 1 (obsolete) • Basic data processing • Byte, word and multi-word load/store • Software interrupt • 26 bit address bus • No Multiply & Coprocessor Support – Version 2 (obsolete) • Multiply • Coprocessor support • 26 bit address bus • First ARM with on-chip Cache (Coprocessor CP15) • SWAP Instruction Introduced – Version 3 • 32 bit address bus • Separate CPSR, SPSR • Add MRS, MSR. Modify exception handler • Add ‘Abort Mode’ and ‘Undef Mode’ • Was Backward Compatible with 26-bit • MUL & MLA – Version 4 • Half word transfer • Introduce THUMB processor state • Add ‘Privileged mode’ for operating system • First fully formalized architecture – Version 5 • Improve ARM/THUMB inter-working • Add CLZ instruction for efficient integer divide • Add software breakpoint • Add more coprocessor support • More tight definition of arithmetic flags