20-10-2016, 02:57 PM
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ABSTRACT:
Digital Signal Processing (DSP) is a field of utmost importance as it performs the processing of digital signals. DSP techniques improves signal quality or extract important information by removing unwanted parts of signal. This extraction of the unwanted parts of the signal is possible with the help of filters.
In this project, FPGA realization of MUX based Multiplier architecture is proposed for FIR filter and discussed in terms of complexity in digital filter implementation. The multiplier usage is avoided by using MUX based multiplier these multiplier is used for constructing direct form FIR filters with signed number representation, the architecture have been implemented using VHDL. FPGA realization of FIR filter architecture such as MUX based multiplier will be discuss. Mux based multiplier have multiplier less architectures to reduce the complexity in the design replaced by shift and add operation respectively.